Abstract: A first input signal is received at a data input of first synchronizer, the first data input to be synchronized to a clock. A second input signal is received at a data input of second synchronizer, the second signal to be synchronized to the clock. Transitions are prevented from being received at a clock input of the first synchronizer and from being received at a the clock input of the second synchronizer in response to the first input signal having the same logic value as a first output signal at an output of the first synchronizer and the second input signal having the same logic value as a second output signal at an output of the second synchronizer.

Abstract: A flexible interrupt controller circuit and methodology are provided which use an interrupt circuit (300) that multiplexes (324) a plurality of interrupt priority registers (321, 322) based on the current context of the system that is identified in mode control selector (326). By using the mode control selector (326) to selectively couple different priority level assignments to a priority encoding module (330), context sensitive switching of the priority levels assigned to each interrupt request can be implemented with reduced latency. The context switch could be based on an OS context ID, power management modes, security modes, and other system defined modes where priority levels would differ. The selected priority level information is used to provide an interrupt request signal (332) which will cause an interrupt to occur in the data processing system.

Abstract: A data processing system may comprise an initiator device having an output whose timing is referenced by a clock input alone corresponding to a first delay along a signaling path. The exemplary data processing system further may further comprise a target device having an input whose timing is referenced by a clock input alone corresponding to a second delay along the signaling path and a system bus interconnected between the initiator device and the target device within the signaling path. The exemplary data processing system may further comprise a dynamic timing bridge coupled to the system bus within the signaling path, wherein responsive to a control signal representative of at least one system characteristic, the dynamic timing bridge performs one selected from the group consisting of (i) inserting a cyclic latency within the signaling path and (ii) not inserting the cyclic latency within the signaling path.

Abstract: A first input signal is received at a data input of first synchronizer, the first data input to be synchronized to a clock. A second input signal is received at a data input of second synchronizer, the second signal to be synchronized to the clock. Transitions are prevented from being received at a clock input of the first synchronizer and from being received at a the clock input of the second synchronizer in response to the first input signal having the same logic value as a first output signal at an output of the first synchronizer and the second input signal having the same logic value as a second output signal at an output of the second synchronizer.

Abstract: A flexible interrupt controller circuit and methodology are provided which use an interrupt circuit (300) that multiplexes (324) a plurality of interrupt priority registers (321, 322) based on the current context of the system that is identified in mode control selector (326). By using the mode control selector (326) to selectively couple different priority level assignments to a priority encoding module (330), context sensitive switching of the priority levels assigned to each interrupt request can be implemented with reduced latency. The context switch could be based on an OS context ID, power management modes, security modes, and other system defined modes where priority levels would differ. The selected priority level information is used to provide an interrupt request signal (332) which will cause an interrupt to occur in the data processing system.

Abstract: A flexible peripheral access protection mechanism within a data processing system (10, 100). In one embodiment, each master (14, 15) within the data processing system (10) includes a corresponding privilege level modifier (70, 74) and corresponding trust attributes (71, 72, 75, 76) for particular bus access types (e.g. read and write accesses). Also, in one embodiment, each peripheral (22, 24) within the data processing system (10) includes a corresponding trust attribute (80, 84), write protect indicator (81, 85), and a privilege protect indicator (82, 86). Therefore, in one embodiment, a bus access by a bus master to a peripheral is allowed when the bus master has the appropriate privilege level and appropriate level of trust required by the peripheral (and the peripheral is not write protected, if the bus access is a write access). Also, through the use of the privilege level modifiers, a the bus master can be forced to a particular privilege level for a particular bus access.

Abstract: A data processing system may comprise an initiator device having an output whose timing is referenced by a clock input alone corresponding to a first delay along a signaling path. The exemplary data processing system further may further comprise a target device having an input whose timing is referenced by a clock input alone corresponding to a second delay along the signaling path and a system bus interconnected between the initiator device and the target device within the signaling path. The exemplary data processing system may further comprise a dynamic timing bridge coupled to the system bus within the signaling path, wherein responsive to a control signal representative of at least one system characteristic, the dynamic timing bridge performs one selected from the group consisting of (i) inserting a cyclic latency within the signaling path and (ii) not inserting the cyclic latency within the signaling path.

Abstract: A method and apparatus is provided for prefetching in a data processing system (10). The data processing system (10) has a bus master (14) and a memory controller (16) coupled to a bus (12). A memory (18) is coupled to the memory controller (16). In the data processing system (14) an address is driven onto the bus (12). Before the address is qualified, data corresponding to the address is prefetched. Prefetching the data before the address is qualified allows prefetches to be accomplished sooner.

Abstract: A system for accessing memory devices includes a processing module coupled to a set of outputs and memory operably coupled to the processing module. The memory stores operational instructions that cause the processing module to perform a plurality of operations. A first one of the plurality of operations includes utilizing a first output to provide a first data lane enable to facilitate accessing of a portion of a first memory storage location associated with a first memory address when in a first mode of operation. A second one of the plurality of operations includes utilizing the first output to provide an address bit of a second memory address to facilitate designation of a second memory storage location when in a second mode of operation.

Abstract: A flexible peripheral access protection mechanism within a data processing system (10, 100), as disclosed herein, allows for a more secure operating environment. In one embodiment, each master (14, 15) within the data processing system (10) includes a corresponding privilege level modifier (70, 74) and corresponding trust attributes (71, 72, 75, 76) for particular bus access types (e.g. read and write accesses). Also, in one embodiment, each peripheral (22, 24) within the data processing system (10) includes a corresponding trust attribute (80, 84), write protect indicator (81, 85), and a privilege protect indicator (82, 86). Therefore, in one embodiment, a bus access by a bus master to a peripheral is allowed when the bus master has the appropriate privilege level and appropriate level of trust required by the peripheral (and the peripheral is not write protected, if the bus access is a write access).

Abstract: A system for accessing memory devices includes a processing module coupled to a set of outputs and memory operably coupled to the processing module. The memory stores operational instructions that cause the processing module to perform a plurality of operations. A first one of the plurality of operations includes utilizing a first output to provide a first data lane enable to facilitate accessing of a portion of a first memory storage location associated with a first memory address when in a first mode of operation. A second one of the plurality of operations includes utilizing the first output to provide an address bit of a second memory address to facilitate designation of a second memory storage location when in a second mode of operation.

Abstract: A memory interface (15) and method of use implements a cache (14) bursting addressing technique which begins a read of main memory (16) in a wrap around mode before automatically switching into a linear addressing mode. The use of two modes which automatically change eliminates an access delay to the main memory when switching modes and optimizes system performance by providing a most critical word first in a first cache line fill and advancing to a sequential address following the first cache line. The sequential address has a higher probability of next use by the processor than any other address. The automatic mode change may be overridden by the memory interface.

Abstract: A memory interface (15) and method of use implements a cache (14) bursting addressing technique which begins a read of main memory (16) in a wrap around mode before automatically switching into a linear addressing mode. The use of two modes which automatically change eliminates an access delay to the main memory when switching modes and optimizes system performance by providing a most critical word first in a first cache line fill and advancing to a sequential address following the first cache line. The sequential address has a higher probability of next use by the processor than any other address. The automatic mode change may be overridden by the memory interface.

Abstract: An analog-to-digital conversion system and method provide selectable data formats for each converted digital result value. Each digital result is stored in a register or table word. Information from a host processor is used to select a desired data format. In one embodiment the address range used to read the digital result serves to select the appropriate data format option, which may be, for example, left-justified or right-justified data, and signed or unsigned data. In another embodiment, one or more command words from the processor are used to select the desired data format.

Abstract: Status flag handling method and apparatus for use in a digital data processing system provide error-resistant operation and simplicity. Two storage elements comprising one bit of a status register are operated such that: a reset places both elements in first predetermined states; a set flag operation places both elements in second predetermined states; a read flag operation alters the state of the second storage element; and a clear flag alters the state of the first storage element if and only if the state of the second storage element has previously been altered by a read flag operation. The flag output corresponds to the state of the first storage element. When implemented with single instructions, inadvertant flag negation and errors due to intervening interrupts are avoided. The read flag operation temporarily disables the set flag mechanism, protecting against setting the flag during a read operation. The flag is always read as asserted prior to being negated.