Patents by Inventor Craig E. Deibele

Craig E. Deibele has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9506953
    Abstract: A measuring system includes an input that emulates a bandpass filter with no signal reflections. A directional coupler connected to the input passes the filtered input to electrically isolated measuring circuits. Each of the measuring circuits includes an amplifier that amplifies the signal through logarithmic functions. The output of the measuring system is an accurate high dynamic range measurement.
    Type: Grant
    Filed: January 17, 2013
    Date of Patent: November 29, 2016
    Assignee: UT-Battelle, LLC
    Inventors: Craig E. Deibele, Douglas E. Curry, Richard W. Dickson, Zaipeng Xie
  • Patent number: 8063649
    Abstract: A measuring system minimizes the parasitic affects of lumped circuit elements. The system includes two or more in-situ interfaces configured to conductively link a source to an internal load and an external load. The in-situ interfaces are linked to a shunt conductor. Two or more linear and dynamic elements conductively link the in-situ interfaces in series. The dynamic elements are configured to overwhelm the parasitic self-capacitance of an input circuit coupled to at least one of the in-situ interfaces. A shield enclosing at least one of the linear and dynamic elements has a conductive surface to fields and electromagnetic interference. The shield has attenuation ratios that substantially dampen the parasitic capacitance between the linear and dynamic elements that bridge some of the in-situ interfaces.
    Type: Grant
    Filed: April 3, 2009
    Date of Patent: November 22, 2011
    Assignee: UT-Battelle, LLC
    Inventors: Craig E. Deibele, George Brian Link, Vladimir V. Peplov
  • Publication number: 20100253366
    Abstract: A measuring system minimizes the parasitic affects of lumped circuit elements. The system includes two or more in-situ interfaces configured to conductively link a source to an internal load and an external load. The in-situ interfaces are linked to a shunt conductor. Two or more linear and dynamic elements conductively link the in-situ interfaces in series. The dynamic elements are configured to overwhelm the parasitic self-capacitance of an input circuit coupled to at least one of the in-situ interfaces. A shield enclosing at least one of the linear and dynamic elements has a conductive surface to fields and electromagnetic interference. The shield has attenuation ratios that substantially dampen the parasitic capacitance between the linear and dynamic elements that bridge some of the in-situ interfaces.
    Type: Application
    Filed: April 3, 2009
    Publication date: October 7, 2010
    Inventors: Craig E. Deibele, George Brian Link, Vladimir V. Peplov
  • Patent number: 7012419
    Abstract: A circuit card stripline Fast Faraday cup quantitatively measures the picosecond time structure of a charged particle beam. The stripline configuration maintains signal integrity, and stitching of the stripline increases the bandwidth. A calibration procedure ensures the measurement of the absolute charge and time structure of the charged particle beam.
    Type: Grant
    Filed: March 26, 2004
    Date of Patent: March 14, 2006
    Assignee: UT-Battelle, LLC
    Inventor: Craig E. Deibele