Patents by Inventor Craig E. Hampel

Craig E. Hampel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110289510
    Abstract: A cache-coherence protocol distributes atomic operations among multiple processors (or processor cores) that share a memory space. When an atomic operation that includes an instruction to modify data stored in the shared memory space is directed to a first processor that does not have control over the address(es) associated with the data, the first processor sends a request, including the instruction to modify the data, to a second processor. Then, the second processor, which already has control of the address(es), modifies the data. Moreover, the first processor can immediately proceed to another instruction rather than waiting for the address(es) to become available.
    Type: Application
    Filed: February 2, 2010
    Publication date: November 24, 2011
    Applicant: RAMBUS INC.
    Inventors: Qi Lin, Liang Peng, Craig E. Hampel, Thomas J. Sheffler, Steven C. Woo, Bohuslav Rychlik
  • Publication number: 20110289245
    Abstract: A chip includes a transmitter circuit and a register provided to store a value representative of an equalization co-efficient setting. The transmitter circuit includes an output driver configured to adjust an output data signal based at least in part on the equalization co-efficient setting.
    Type: Application
    Filed: August 2, 2011
    Publication date: November 24, 2011
    Inventors: Mark A. Horowitz, Richard M. Barth, Craig E. Hampel, Alfredo Moncayo, Kevin S. Donnelly, Jared L. Zerbe
  • Patent number: 8060665
    Abstract: An integrated circuit input/output interface with empirically determined delay matching is disclosed. In one embodiment, the integrated circuit input/output interface uses empirical information of signal traces coupled to the integrated circuit to adjust a transmit/receive clock of each pin of the interface so as to compensate for delay mismatches caused by differences in signal trace lengths. In one embodiment, values representative of the empirical information are stored for use by the integrated circuit to generate trace-specific signals so as to compensate for delay differences that are at least partially caused by unmatched signal trace lengths. The empirical information, in one embodiment, includes signal flight time of each signal trace, which can be pre-measured or pre-calculated from known signal trace lengths. The empirical information, in another embodiment, includes trace-specific phase offset values calculated from pre-calculated or pre-measured signal flight times or signal trace lengths.
    Type: Grant
    Filed: June 12, 2008
    Date of Patent: November 15, 2011
    Assignee: Rambus Inc.
    Inventors: Craig E. Hampel, Scott C. Best
  • Patent number: 8059476
    Abstract: Disclosed herein are embodiments of an asynchronous memory device that use internal delay elements to enable memory access pipelining. In one embodiment, the delay elements are responsive to an input load control signal, and are calibrated with reference to periodically received timing pulses. Different numbers of the delay elements are configured to produce different asynchronous delays and to strobe sequential pipeline elements of the memory device.
    Type: Grant
    Filed: November 9, 2010
    Date of Patent: November 15, 2011
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, Ely K. Tsern, Craig E. Hampel, Donald C. Stark
  • Publication number: 20110248761
    Abstract: Apparatus and methods are disclosed for adjusting phase of data signals to compensate for phase-offset variations between devices during normal operation. The phase of data signals are adjusted individually in each transmit data unit and receive data unit across multiple data slices with a common set of phase vector clock signals and a corresponding clock cycle count signal. The transmission of signal information between a first device (such as a memory controller) and a second device (such as a memory component) occurs without errors even when the accumulated delays between the first device and second device change by a half symbol time interval or more during operation of the system. The apparatus reduces the circuitry required, such as phase-lock-loops, for individually adjusting the phase of each transmit data unit and receive data unit across multiple data slices, which in turn results in reduction in complexity and cost of the system.
    Type: Application
    Filed: June 17, 2011
    Publication date: October 13, 2011
    Inventors: Craig E. Hampel, Richard E. Perego, Stefanos S. Sidiropoulos, Ely K. Tsern, Fredrick A. Ware
  • Patent number: 8028144
    Abstract: A memory module having reduced access granularity. The memory module includes a substrate having signal lines thereon that form a control path and first and second data paths, and further includes first and second memory devices coupled in common to the control path and coupled respectively to the first and second data paths. The first and second memory devices include control circuitry to receive respective first and second memory access commands via the control path and to effect concurrent data transfer on the first and second data paths in response to the first and second memory access commands.
    Type: Grant
    Filed: February 24, 2009
    Date of Patent: September 27, 2011
    Assignee: RAMBUS Inc.
    Inventors: Craig E. Hampel, Frederick A. Ware
  • Patent number: 8018789
    Abstract: The memory module includes front and back faces. Multiple devices are disposed on each of the faces. A first control line serially connects a first group of devices on both the front and back faces so that the first group of devices commonly contribute multiple bits to a data bus. A second control line serially connects a second group of devices on both the front and back faces so that the second group of devices commonly contribute multiple bits to a data bus.
    Type: Grant
    Filed: September 10, 2009
    Date of Patent: September 13, 2011
    Assignee: Rambus Inc.
    Inventors: Steven C. Woo, Craig E. Hampel
  • Patent number: 8019958
    Abstract: In a method of controlling a memory device, the following is conveyed over a first set of interconnect resources: a first command that specifies activation of a row of memory cells; a second command that specifies a write operation, wherein write data is written to the row; a bit that specifies whether precharging occurs after the write data is written; and a code that specifies whether data mask information will be issued for the write operation. If the code specifies that the information will be issued, then the information, which specifies whether to selectively write portions of the write data, is conveyed over the first set of interconnect resources after conveying the code. The write data to be written in connection with the write operation is conveyed over a second set of interconnect resources that is separate from the first set of interconnect resources.
    Type: Grant
    Filed: September 3, 2010
    Date of Patent: September 13, 2011
    Assignee: Rambus Inc.
    Inventors: Richard M. Barth, Frederick A. Ware, Donald C. Stark, Craig E. Hampel, Paul G. Davis, Abhijit M. Abhyankar, James A. Gasbarre, David Nguyen
  • Patent number: 8001305
    Abstract: A dynamic random access memory device (DRAM) receiver circuit includes an input to receive a data signal, and also includes decision circuitry to make a decision about the received data signal based on a present sampled data signal and a coefficient value corresponding to at least one of a previously sampled data signals.
    Type: Grant
    Filed: June 5, 2009
    Date of Patent: August 16, 2011
    Assignee: Rambus Inc.
    Inventors: Mark A. Horowitz, Richard M. Barth, Craig E. Hampel, Alfredo Moncayo, Kevin S. Donnelly, Jared L. Zerbe
  • Patent number: 7986584
    Abstract: A memory device having a memory core is described. The memory device includes a clock receiver circuit, a first interface to receive a read command, a data interface, and a second interface to receive power mode information. The data interface is separate from the first interface. The second interface is separate from the first interface and the data interface. The memory device has a plurality of power modes, including a first mode in which the clock receiver circuit, first interface, and data interface are turned off; a second mode in which the clock receiver is turned on and the first interface and data interface are turned off; and a third mode in which the clock receiver and first interface are turned on. In the third mode, the data interface is turned on when the first interface receives the command, to output data in response to the command.
    Type: Grant
    Filed: October 29, 2009
    Date of Patent: July 26, 2011
    Assignee: Rambus Inc.
    Inventors: Ely K. Tsern, Richard M. Barth, Craig E. Hampel, Donald C. Stark
  • Patent number: 7965567
    Abstract: Apparatus and methods are disclosed for adjusting phase of data signals to compensate for phase-offset variations between devices during normal operation. The phase of data signals are adjusted individually in each transmit data unit and receive data unit across multiple data slices with a common set of phase vector clock signals and a corresponding clock cycle count signal. The transmission of signal information between a first device (such as a memory controller) and a second device (such as a memory component) occurs without errors even when the accumulated delays between the first device and second device change by a half symbol time interval or more during operation of the system. The apparatus reduces the circuitry required, such as phase-lock-loops, for individually adjusting the phase of each transmit data unit and receive data unit across multiple data slices, which in turn results in reduction in complexity and cost of the system.
    Type: Grant
    Filed: September 14, 2007
    Date of Patent: June 21, 2011
    Assignee: Rambus Inc.
    Inventors: Craig E. Hampel, Richard E. Perego, Stefanos S. Sidiropoulos, Ely K. Tsern, Fredrick A. Ware
  • Publication number: 20110093669
    Abstract: A method of operating a memory component that includes a memory core includes receiving, from external control lines, a write command that specifies a write operation. The write command is stored for a first time period after receiving the write command. After the first time period, the write operation is initiated in response to the write command. During the write operation, unmasked portions of received data are written to the memory core, where the unmasked portions of the data are bits of the data that are identified by received mask information as not being masked.
    Type: Application
    Filed: December 21, 2010
    Publication date: April 21, 2011
    Inventors: Paul G. Davis, Frederick A. Ware, Craig E. Hampel
  • Publication number: 20110090755
    Abstract: A memory device having a memory core is described. The memory device includes a clock receiver circuit, a first interface to receive a read command, a data interface, and a second interface to receive power mode information. The data interface is separate from the first interface. The second interface is separate from the first interface and the data interface. The memory device has a plurality of power modes, including a first mode in which the clock receiver circuit, first interface, and data interface are turned off; a second mode in which the clock receiver is turned on and the first interface and data interface are turned off; and a third mode in which the clock receiver and first interface are turned on. In the third mode, the data interface is turned on when the first interface receives the command, to output data in response to the command.
    Type: Application
    Filed: December 21, 2010
    Publication date: April 21, 2011
    Inventors: Ely K. Tsern, Richard M. Barth, Craig E. Hampel, Donald C. Stark
  • Patent number: 7916570
    Abstract: In a memory device having a memory core and a signal interface, receiving a command that specifies at least a portion of a memory access. During the memory access, transferring data between the memory core and the signaling interface, and transferring the data between the signaling interface and an external signal path, and prior to transferring the data between the signaling interface and the external signal path, receiving enable information to selectively enable at least a first memory resource and a second memory resource, wherein each of the first memory resource and the second memory resource performs a control function associated with the memory access.
    Type: Grant
    Filed: January 23, 2008
    Date of Patent: March 29, 2011
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, Ely K. Tsern, Craig E. Hampel
  • Publication number: 20110055509
    Abstract: Disclosed herein are embodiments of an asynchronous memory device that use internal delay elements to enable memory access pipelining. In one embodiment, the delay elements are responsive to an input load control signal, and are calibrated with reference to periodically received timing pulses. Different numbers of the delay elements are configured to produce different asynchronous delays and to strobe sequential pipeline elements of the memory device.
    Type: Application
    Filed: November 9, 2010
    Publication date: March 3, 2011
    Inventors: Frederick A. Ware, Ely K. Tsern, Craig E. Hampel, Donald C. Stark
  • Publication number: 20110016278
    Abstract: A memory module includes a substrate having signal lines thereon that form a control path and a plurality of data paths. A plurality of memory devices are mounted on the substrate. Each memory device is coupled to the control path and to a distinct data path. The memory module includes control circuitry to enable each memory device to process a distinct respective memory access command in a succession of memory access commands and to output data on the distinct data path in response to the processed memory access command.
    Type: Application
    Filed: March 5, 2009
    Publication date: January 20, 2011
    Inventors: Frederick Ware, Craig E. Hampel, Ian Shaeffer, Scott C. Best
  • Patent number: 7870357
    Abstract: A method of operating a memory component that includes a memory core includes receiving, from external control lines, a write command that specifies a write operation. The write command is stored for a first time period after receiving the write command. After the first time period, the write operation is initiated in response to the write command. During the write operation, unmasked portions of received data are written to the memory core, where the unmasked portions of the data are bits of the data that are identified by received mask information as not being masked.
    Type: Grant
    Filed: September 30, 2008
    Date of Patent: January 11, 2011
    Assignee: Rambus Inc.
    Inventors: Paul G. Davis, Frederick A. Ware, Craig E. Hampel
  • Publication number: 20100332719
    Abstract: In a method of controlling a memory device, the following is conveyed over a first set of interconnect resources: a first command that specifies activation of a row of memory cells; a second command that specifies a write operation, wherein write data is written to the row; a bit that specifies whether precharging occurs after the write data is written; and a code that specifies whether data mask information will be issued for the write operation. If the code specifies that the information will be issued, then the information, which specifies whether to selectively write portions of the write data, is conveyed over the first set of interconnect resources after conveying the code. The write data to be written in connection with the write operation is conveyed over a second set of interconnect resources that is separate from the first set of interconnect resources.
    Type: Application
    Filed: September 3, 2010
    Publication date: December 30, 2010
    Inventors: Richard M. Barth, Frederick A. Ware, Donald C. Stark, Craig E. Hampel, Paul G. Davis, Abhijit M. Abhyankar, James A. Gasbarre, David Nguyen
  • Patent number: 7830735
    Abstract: Disclosed herein are embodiments of an asynchronous memory device that use internal delay elements to enable memory access pipelining. In one embodiment, the delay elements are responsive to an input load control signal, and are calibrated with reference to periodically received timing pulses. Different numbers of the delay elements are configured to produce different asynchronous delays and to strobe sequential pipeline elements of the memory device.
    Type: Grant
    Filed: May 4, 2009
    Date of Patent: November 9, 2010
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, Ely K. Tsern, Craig E. Hampel, Donald C. Stark
  • Patent number: 7793039
    Abstract: A semiconductor memory device includes a memory core, a first interface to receive write data from a first set of interconnect resources, and a second interface, separate from the first interface, to receive from a second set of interconnect resources a column address and a first code. The column address is associated with the write data and identifies a column of the memory core in which to store the write data. The first code indicates whether the write data is selectively masked by data mask information. If the first code indicates that the write data is selectively masked, the second interface is to receive data mask information specifying whether to selectively write portions of the write data to the memory core.
    Type: Grant
    Filed: January 6, 2009
    Date of Patent: September 7, 2010
    Assignee: Rambus Inc.
    Inventors: Richard M. Barth, Frederick A. Ware, Donald C. Stark, Craig E. Hampel, Paul G. Davis, Abhijit M. Abhyankar, James A. Gasbarro, David Nguyen