Abstract: A wing lock and deployment apparatus for an air launched vehicle includes a driver acted on by a single linear actuation event. The disclosed wing lock and deployment apparatus is capable of unlocking deployable wings of an air launched vehicle, deploying deployable wings of the air launched vehicle from a stored position, and locking deployable wings of the air launched vehicle in a deployed position in sequential order with the one single linear actuation event.

Abstract: A clock generator system (400) includes a phase locked loop (PLL) (402), a first clock generator (404), and a second clock generator (406). The PLL (402) includes a first output configured to provide a first clock signal at a first frequency and a second output configured to provide a second clock signal at the first frequency. The second clock signal is out-of-phase with the first clock signal. An output of the first clock generator (404) is configured to provide a first generated clock signal whose effective frequency is based on both the first and second clock signals and a first mode signal. An output of the second clock generator (406) is configured to provide a second generated clock signal whose effective frequency is based on both the first and second clock signals and a second mode signal.

Abstract: A processor (400) includes a clock source (402), a central processing unit (CPU) (408), and a clock generator (404). The clock source (402) includes an output for providing a periodic clock signal. The CPU (408) includes an input for receiving a CPU clock signal. The clock generator (404) includes a first input coupled to the output of the clock source (402), a second input for receiving a mode signal that indicates an output frequency, and an output coupled to the input of the CPU (408). The clock generator (404) provides the CPU clock signal using periodic pulse skipping such that the CPU clock signal has a number of transitions over a unit of time corresponding to the output frequency.

Abstract: A clock generator (622) includes a first circuit (812) and a second circuit (814). The first circuit (812) includes a first clock input configured to receive a first clock signal at a first frequency, a second clock input configured to receive a second clock signal at the first frequency, and an output. The second clock signal is out-of-phase with the first clock signal. The second circuit (814) is coupled to the first circuit (812) and includes a mode signal input configured to receive a mode signal. The output of the first circuit (812) is configured to provide a generated clock signal whose effective frequency is based on the first and second clock signals and the mode signal.

Abstract: A processor (400) includes a clock source (402), a central processing unit (CPU) (408), and a clock generator (404). The clock source (402) includes an output for providing a periodic clock signal. The CPU (408) includes an input for receiving a CPU clock signal. The clock generator (404) includes a first input coupled to the output of the clock source (402), a second input for receiving a mode signal that indicates an output frequency, and an output coupled to the input of the CPU (408). The clock generator (404) provides the CPU clock signal using periodic pulse skipping such that the CPU clock signal has a number of transitions over a unit of time corresponding to the output frequency.

Abstract: A clock generator (622) includes a first circuit (812) and a second circuit (814). The first circuit (812) includes a first clock input configured to receive a first clock signal at a first frequency, a second clock input configured to receive a second clock signal at the first frequency, and an output. The second clock signal is out-of-phase with the first clock signal. The second circuit (814) is coupled to the first circuit (812) and includes a mode signal input configured to receive a mode signal. The output of the first circuit (812) is configured to provide a generated clock signal whose effective frequency is based on the first and second clock signals and the mode signal.

Abstract: A clock generator system (400) includes a phase locked loop (PLI,) (402), a first clock generator (404), and a second clock generator (406). The PLL (402) includes a first output configured to provide a first clock signal at a first frequency and a second output configured to provide a second clock signal at the first frequency. The second clock signal is out-of-phase with the first clock signal. An output of the first clock generator (404) is configured to provide a first generated clock signal whose effective frequency is based on both the first and second clock signals and a first mode signal. An output of the second clock generator (406) is configured to provide a second generated clock signal whose effective frequency is based on both the first and second clock signals and a second mode signal.