Patents by Inventor Craig Edward Hampel
Craig Edward Hampel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20020087790Abstract: A system and method for performing data transfers within a computer system is provided. The system includes a controller configured to dynamically adjust the interleave of the communications required to perform a series of data transfer operations to maximize utilization of the channel over which the communications are to be performed. The controller is able to vary the time interval between the transmission of control information that requests a data transfer and the performance of the data transfer by signaling the beginning of the data transfer with a strobe signal sent separate from the control information. The controller is able to defer the determination of how much data will be transferred in the operation by initiating the termination of a data transfer with a termination signal. The method provides a technique for distinguishing between identical control signals that are carried on the same line.Type: ApplicationFiled: March 8, 2002Publication date: July 4, 2002Inventors: Richard Maurice Barth, Frederick Abbot Ware, John Bradly Dillon, Donald Charles Stark, Craig Edward Hampel, Matthew Murdy Griffin
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Patent number: 6405296Abstract: A method and system for transferring information within a computer system is provided. The system includes a memory device that has a lower power mode in which data transfer circuitry is not driven by a clock signal, and a higher power mode in which data transfer circuitry is driven by a clock signal. The system further includes a memory controller that sends control signals to the memory device to initiate a data transfer transaction. The memory device receives the control signals asynchronously, and assumes the second mode in response to one of the control signals. While the memory device is in the second mode, the memory controller sends a control signal to identify a particular clock cycle. The memory device synchronously transfers the data. The memory device determines when to begin the data transfer based on the identified clock cycle and the type of data transfer that has been specified.Type: GrantFiled: August 11, 2000Date of Patent: June 11, 2002Assignee: Rambus Inc.Inventors: Richard Maurice Barth, Mark Alan Horowitz, Craig Edward Hampel, Frederick Abbot Ware
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Publication number: 20020027447Abstract: An apparatus for reducing worst-case power consumption. The apparatus includes a first signal that has signal transitions. A circuit path is provided for transmitting a second signal through buffered circuit sections. Logic circuitry is coupled to the circuit path and to the first signal. The logic circuitry uses the first signal to reduce a sum of signal transitions of the second signal as the second signal propagates from one buffered section of the circuit path to another buffered section of the circuit path in order to reduce worst-case power consumption.Type: ApplicationFiled: August 7, 2001Publication date: March 7, 2002Applicant: Rambus, Inc.Inventors: Craig Edward Hampel, Donald Victor Perino
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Publication number: 20020010832Abstract: A method is described for providing a memory with a serial sequence of write enable signals that are offset in time with respect to respective data received by a plurality of data inputs of the memory. A memory is also described with an array for data storage, a plurality of data input pins, and a separate pin for receiving either additional data or a serial sequence of write enable signals applicable to data received by the plurality of data input pins. The additional data that the separate pin can receive includes, for example, error detection and correction (EDC) information. A method is also described for multiplexing write enable information and error detection and correction information.Type: ApplicationFiled: September 28, 2001Publication date: January 24, 2002Inventors: Frederick Abbott Ware, Craig Edward Hampel, Donald Charles Stark, Matthew Murdy Griffin
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Publication number: 20020004865Abstract: A system and method for performing data transfers within a computer system is provided. The system includes a controller configured to dynamically adjust the interleave of the communications required to perform a series of data transfer operations to maximize utilization of the channel over which the communications are to be performed. The controller is able to vary the time interval between the transmission of control information that requests a data transfer and the performance of the data transfer by signaling the beginning of the data transfer with a strobe signal sent separate from the control information. The controller is able to defer the determination of how much data will be transferred in the operation by initiating the termination of a data transfer with a termination signal. The method provides a technique for distinguishing between identical control signals that are carried on the same line.Type: ApplicationFiled: May 29, 2001Publication date: January 10, 2002Inventors: Richard Maurice Barth, Frederick Abbot Ware, John Bradly Dillon, Donald Charles Stark, Craig Edward Hampel, Matthew Murdy Griffin
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Publication number: 20010042182Abstract: A method and system for transferring information within a computer system is provided. The system includes a memory device that has a lower power mode in which data transfer circuitry is not driven by a clock signal, and a higher power mode in which data transfer circuitry is driven by a clock signal. The system further includes a memory controller that sends control signals to the memory device to initiate a data transfer transaction. The memory device receives the control signals asynchronously, and assumes the second mode in response to one of the control signals. While the memory device is in the second mode, the memory controller sends a control signal to identify a particular clock cycle. The memory device synchronously transfers the data. The memory device determines when to begin the data transfer based on the identified clock cycle and the type of data transfer that has been specified.Type: ApplicationFiled: May 23, 2000Publication date: November 15, 2001Inventors: Richard Maurice Barth, Mark Alan Horowitz, Craig Edward Hampel, Frederick Abbot Ware
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Publication number: 20010034810Abstract: A method is described for providing a memory with a serial sequence of write enable signals that are offset in time with respect to respective data received by a plurality of data inputs of the memory. A memory is also described with an array for data storage, a plurality of data input pins, and a separate pin for receiving either additional data or a serial sequence of write enable signals applicable to data received by the plurality of data input pins. The additional data that the separate pin can receive includes, for example, error detection and correction (EDC) information. A method is also described for multiplexing write enable information and error detection and correction information.Type: ApplicationFiled: May 14, 2001Publication date: October 25, 2001Inventors: Frederick Abbott Ware, Craig Edward Hampel, Donald Charles Stark, Matthew Murdy Griffin
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Patent number: 6304104Abstract: An apparatus for reducing worst-case power consumption. The apparatus includes a first signal that has signal transitions. A circuit path is provided for transmitting a second signal through buffered circuit sections. Logic circuitry is coupled to the circuit path and to the first signal. The logic circuitry uses the first signal to reduce a sum of signal transitions of the second signal as the second signal propagates from one buffered section of the circuit path to another buffered section of the circuit path in order to reduce worst-case power consumption.Type: GrantFiled: September 13, 1999Date of Patent: October 16, 2001Assignee: Rambus, Inc.Inventors: Craig Edward Hampel, Donald Victor Perino
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Patent number: 6266737Abstract: A method is described for providing a memory with a serial sequence of write enable signals that are offset in time with respect to respective data received by a plurality of data inputs of the memory. A memory is also described with an array for data storage, a plurality of data input pins, and a separate pin for receiving either additional data or a serial sequence of write enable signals applicable to data received by the plurality of data input pins. The additional data that the separate pin can receive includes, for example, error detection and correction (EDC) information. A method is also described for multiplexing write enable information and error detection and correction information.Type: GrantFiled: January 10, 2000Date of Patent: July 24, 2001Assignee: Rambus Inc.Inventors: Frederick Abbott Ware, Craig Edward Hampel, Donald Charles Stark, Matthew Murdy Griffin
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Patent number: 6209071Abstract: A method and system for transferring information within a computer system is provided. The system includes a memory device that has a lower power mode in which data transfer circuitry is not driven by a clock signal, and a higher power mode in which data transfer circuitry is driven by a clock signal. The system further includes a memory controller that sends control signals to the memory device to initiate a data transfer transaction. The memory device receives the control signals asynchronously, and assumes the second mode in response to one of the control signals. While the memory device is in the second mode, the memory controller sends a control signal to identify a particular clock cycle. The memory device synchronously transfers the data. The memory device determines when to begin the data transfer based on the identified clock cycle and the type of data transfer that has been specified.Type: GrantFiled: May 7, 1996Date of Patent: March 27, 2001Assignee: Rambus Inc.Inventors: Richard Maurice Barth, Mark Alan Horowitz, Craig Edward Hampel, Frederick Abbot Ware
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Patent number: 6122688Abstract: A system and method for performing data transfers within a computer system is provided. The system includes a controller configured to dynamically adjust the interleave of the communications required to perform a series of data transfer operations to maximize utilization of the channel over which the communications are to be performed. The controller is able to vary the time interval between the transmission of control information that requests a data transfer and the performance of the data transfer by signaling the beginning of the data transfer with a strobe signal sent separate from the control information. The controller is able to defer the determination of how much data will be transferred in the operation by initiating the termination of a data transfer with a termination signal. The method provides a technique for distinguishing between identical control signals that are carried on the same line.Type: GrantFiled: November 26, 1997Date of Patent: September 19, 2000Assignee: Rambus Inc.Inventors: Richard Maurice Barth, Frederick Abbot Ware, John Bradly Dillon, Donald Charles Stark, Craig Edward Hampel, Matthew Murdy Griffin
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Patent number: 6035369Abstract: A method is described for providing a memory with a serial sequence of write enable signals that are offset in time with respect to respective data received by a plurality of data inputs of the memory. A memory is also described with an array for data storage, a plurality of data input pins, and a separate pin for receiving either additional data or a serial sequence of write enable signals applicable to data received by the plurality of data input pins. The additional data that the separate pin can receive includes, for example, error detection and correction (EDC) information. A method is also described for multiplexing write enable information and error detection and correction information.Type: GrantFiled: October 19, 1995Date of Patent: March 7, 2000Assignee: Rambus Inc.Inventors: Frederick Abbott Ware, Craig Edward Hampel, Donald Charles Stark, Matthew Murdy Griffin
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Patent number: 5966731Abstract: A system and method for performing data transfers within a computer system is provided. The system includes a controller configured to dynamically adjust the interleave of the communications required to perform a series of data transfer operations to maximize utilization of the channel over which the communications are to be performed. The controller is able to vary the time interval between the transmission of control information that requests a data transfer and the performance of the data transfer by signaling the beginning of the data transfer with a strobe signal sent separate from the control information. The controller is able to defer the determination of how much data will be transferred in the operation by initiating the termination of a data transfer with a termination signal. The method provides a technique for distinguishing between identical control signals that are carried on the same line.Type: GrantFiled: November 26, 1997Date of Patent: October 12, 1999Assignee: Rambus, Inc.Inventors: Richard Maurice Barth, Frederick Abbot Ware, John Bradly Dillon, Donald Charles Stark, Craig Edward Hampel, Matthew Murdy Griffin
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Patent number: 5913046Abstract: A system and method for performing data transfers within a computer system is provided. The system includes a controller configured to dynamically adjust the interleave of the communications required to perform a series of data transfer operations to maximize utilization of the channel over which the communications are to be performed. The controller is able to vary the time interval between the transmission of control information that requests a data transfer and the performance of the data transfer by signaling the beginning of the data transfer with a strobe signal sent separate from the control information. The controller is able to defer the determination of how much data will be transferred in the operation by initiating the termination of a data transfer with a termination signal. The method provides a technique for distinguishing between identical control signals that are carried on the same line.Type: GrantFiled: November 26, 1997Date of Patent: June 15, 1999Assignee: Rambus Inc.Inventors: Richard Maurice Barth, Frederick Abbot Ware, John Bradly Dillon, Donald Charles Stark, Craig Edward Hampel, Matthew Murdy Griffin
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Patent number: 5748914Abstract: A system and method for performing data transfers within a computer system is provided. The system includes a controller configured to dynamically adjust the interleave of the communications required to perform a series of data transfer operations to maximize utilization of the channel over which the communications are to be performed. The controller is able to vary the time interval between the transmission of control information that requests a data transfer and the performance of the data transfer by signaling the beginning of the data transfer with a strobe signal sent separate from the control information. The controller is able to defer the determination of how much data will be transferred in the operation by initiating the termination of a data transfer with a termination signal. The method provides a technique for distinguishing between identical control signals that are carried on the same line.Type: GrantFiled: October 19, 1995Date of Patent: May 5, 1998Assignee: Rambus, Inc.Inventors: Richard Maurice Barth, Frederick Abbot Ware, John Bradly Dillon, Donald Charles Stark, Craig Edward Hampel, Matthew Murdy Griffin