Patents by Inventor Craig Franklin Deaton
Craig Franklin Deaton has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11580284Abstract: The present disclosure relates to a method for electronic circuit design. Embodiments may include receiving, using a processor, an electronic circuit design and performing a deadlock check on the electronic circuit design using a using a linear temporal logic property and a proof engine. Embodiments may further include analyzing a counterexample associated with the electronic circuit design for a loop escape condition, wherein analyzing includes proving a cover trace of a liveness obligation. If the loop escape condition is reachable from the counterexample, embodiments may include extracting one or more events associated with the loop escape condition and adding a waiver constraint to the deadlock check to force a no deadlock outcome.Type: GrantFiled: January 6, 2021Date of Patent: February 14, 2023Assignee: Cadence Design Systems, Inc.Inventors: Craig Franklin Deaton, Christopher William Komar, Lars Lundgren
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Patent number: 11138355Abstract: A formal verification EDA application can be configured to receive a circuit design of an IC chip, the circuit design of the IC chip including a list of properties for the IC chip. The list of properties includes a list of covers for the IC chip. The formal verification engine can also execute a formal verification of the IC chip. Results of the formal verification identifies a subset of covers of the list of covers that are unreachable. The formal verification engine can further execute a root cause search for a selected cover in the subset of covers that are unreachable. The root cause search selectively adds and removes cutpoints to signals in the circuit design to identify a root cause for the selected cover being unreachable. The root cause comprises a signal in the circuit design that is upstream from the selected cover.Type: GrantFiled: November 16, 2020Date of Patent: October 5, 2021Assignee: CADENCE DESIGN SYSTEMS, INC.Inventors: Craig Franklin Deaton, Maayan Ziv, Kanwar Pal Singh, Nizar Hanna, Gasob Mazzawi
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Patent number: 10540467Abstract: The present disclosure relates to a method for electronic circuit design. Embodiments may include receiving, using a processor, an electronic circuit design and identifying at least one combinational loop associated with the electronic circuit design. Embodiments may also include extracting, for each component of the loop, a set of logic conditions and modeling the at least one combinational loop. Embodiments may further include providing a graphical user interface configured to display one or more constraint candidates and determining whether or not a conflict exists between constraint candidates. Embodiments may also include ranking the constraint candidates, based upon, at least in part, a number of loops disabled and one or more disabled loop characteristics.Type: GrantFiled: April 3, 2018Date of Patent: January 21, 2020Assignee: Cadence Design Systems, Inc.Inventors: Craig Franklin Deaton, Abner Luis Panho Marciano, Matheus Nogueira Fonseca, Ronalu Augusta Nunes Barcelos, Fabiano Cruz Peixoto
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Patent number: 10380312Abstract: The present disclosure relates to a method for electronic design verification. Embodiments may include receiving, using at least one processor, an electronic design and identifying one or more assumptions associated with the electronic design that are mutually in conflict. Embodiments may further include grouping the one or more assumptions that are mutually in conflict into a conflicting group of assumptions and iteratively disabling at least one of the conflicting group of assumptions. Embodiments may include generating at least one trace pair depicting a scenario where an assumption from a disabled set holds in a first trace but is violated in a second trace. Embodiments may further include identifying at least one signal associated with the first trace and at least one signal associated with the second trace and comparing the at least one signal associated with the first trace and the at least one signal associated with the second trace.Type: GrantFiled: December 7, 2016Date of Patent: August 13, 2019Assignee: Cadence Design Systems, Inc.Inventors: Craig Franklin Deaton, Lars Lundgren
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Patent number: 9372949Abstract: A model checking tool, which is used to test a circuit design, attempts to reach a target state from an initial state in the state-space of the circuit design using one or more intermediate states. Through an iterative process, the tool identifies intermediate states in the state-space of the circuit design that are used to generate starting states for subsequent iterations of the process. The intermediate states help to restrict the scope of the state-space search to reduce the time and memory requirements needed to reach the target state. The model checking tool also explores the state-space in parallel from a subset of computed restart states, which reduces the possibility of bypassing any essential intermediate or target states.Type: GrantFiled: October 25, 2011Date of Patent: June 21, 2016Assignee: Cadence Design Systems, Inc.Inventors: Ziyad Hanna, Craig Franklin Deaton, Kathryn Drews Kranen, Björn Håkan Hjort, Lars Lundgren
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Patent number: 8831925Abstract: An executable circuit design is used to generate waveforms, from which behaviors of the circuit are captured. The behaviors and various combinations thereof can then be saved in a database, along with descriptions and other metadata about them, thereby generating a behavioral index of the circuit design code. Behavioral indexing of circuit designs allows a user to maintain an indexed behavior database, track changes in behaviors as the circuit design's executable description evolves, and figure out how the executable description can be reused in different projects. When applied to digital design development, it facilities the current design and verification effort, as well as design reuse down the line.Type: GrantFiled: June 9, 2010Date of Patent: September 9, 2014Assignee: Jasper Design Automation, Inc.Inventors: Kathryn Drews Kranen, Chung-Wah Norris Ip, Rajeev Kumar Ranjan, Lawrence Loh, Beth C. Isaksen, Yann Alain Antonioli, Craig Franklin Deaton
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Patent number: 8731894Abstract: An executable circuit design is used to generate waveforms, from which behaviors of the circuit are captured. The behaviors and various combinations thereof can then be saved in a database, along with descriptions and other metadata about them, thereby generating a behavioral index of the circuit design code. Behavioral indexing of circuit designs allows a user to maintain an indexed behavior database, track changes in behaviors as the circuit design's executable description evolves, and figure out how the executable description can be reused in different projects. When applied to digital design development, it facilities the current design and verification effort, as well as design reuse down the line.Type: GrantFiled: September 14, 2012Date of Patent: May 20, 2014Assignee: Jasper Design Automation, Inc.Inventors: Kathryn Drews Kranen, Chung-Wah Norris Ip, Rajeev Kumar Ranjan, Lawrence Loh, Beth C. Isaksen, Yann Alain Antonioli, Craig Franklin Deaton
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Patent number: 8671373Abstract: A first signal trace is received including signal values satisfying a target event. A first trace signature is generated describing a portion of the first signal trace that causes the target event to occur. A second signal trace is generated that includes signal values satisfying the target event. A second trace signature is generated describing a portion of the second signal trace that causes the target event to occur. Differential signal events are determined that differentiate the first trace signature from the second trace signature. The differential signal events are events from the first signal trace that cause the target event to occur, but do not appear in the second trace signature. The process can be repeated to receive a plurality of signal traces, and to generate a plurality of signal traces. The differential signal events are indexed in a datastore in association with the signal traces.Type: GrantFiled: November 9, 2012Date of Patent: March 11, 2014Assignee: Jasper Design Automation, Inc.Inventor: Craig Franklin Deaton
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Patent number: 8630824Abstract: An executable circuit design is used to generate waveforms, from which behaviors of the circuit are captured. The behaviors and various combinations thereof can then be saved in a database, along with descriptions and other metadata about them, thereby generating a behavioral index of the circuit design code. Behavioral indexing of circuit designs allows a user to maintain an indexed behavior database, track changes in behaviors as the circuit design's executable description evolves, and figure out how the executable description can be reused in different projects. When applied to digital design development, it facilities the current design and verification effort, as well as design reuse down the line.Type: GrantFiled: June 9, 2010Date of Patent: January 14, 2014Assignee: Jasper Design Automation, Inc.Inventors: Chung-Wah Norris Ip, Kathryn Drews Kranen, Rajeev Kumar Ranjan, Beth C. Isaksen, Karl Stefan Esbjörner, Craig Franklin Deaton