Patents by Inventor Craig Fullerton

Craig Fullerton has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8781779
    Abstract: An improved method and apparatus for automatically aligning probe pins to the test or bond pads of semiconductor devices under changing conditions. In at least one embodiment, a dynamic model is used to predict an impact of changing conditions to wafer probing process. This reduces the need for frequent measurements and calibrations during probing and testing, thereby increasing the number of dice that can be probed and tested in a given period of time and increasing the accuracy of probing at the same time. Embodiments of the present invention also make it possible to adjust positions of probe pins and pads in response to the changing conditions while they are in contact with each other.
    Type: Grant
    Filed: November 9, 2012
    Date of Patent: July 15, 2014
    Assignee: FormFactor, Inc.
    Inventors: Richard James Casler, Jr., Fenglei Du, Stephen Craig Fullerton
  • Publication number: 20130326362
    Abstract: Among other things, we describe enabling two or more users to share a workspace that is dynamically populated by artifacts of electronic communications among the users that are expressed in a form of at least one of social network posts and email messages, and in which the users can interact using the artifacts in any of the forms.
    Type: Application
    Filed: June 5, 2012
    Publication date: December 5, 2013
    Inventors: Neil Hamilton Murray, Craig Fullerton, David Goldberg, Simon Paul Tyler, Nathaniel Borenstein, Peter Bauer
  • Patent number: 8311758
    Abstract: An improved method and apparatus for automatically aligning probe pins to the test or bond pads of semiconductor devices under changing conditions. In at least one embodiment, a dynamic model is used to predict an impact of changing conditions to wafer probing process. This reduces the need for frequent measurements and calibrations during probing and testing, thereby increasing the number of dice that can be probed and tested in a given period of time and increasing the accuracy of probing at the same time. Embodiments of the present invention also make it possible to adjust positions of probe pins and pads in response to the changing conditions while they are in contact with each other.
    Type: Grant
    Filed: January 18, 2006
    Date of Patent: November 13, 2012
    Assignee: FormFactor, Inc.
    Inventors: Richard James Casler, Jr., Fenglei Du, Stephen Craig Fullerton
  • Patent number: 5311122
    Abstract: An RF test equipment and wire bond interface circuit (150) for facilitating the on-wafer (100) testing of integrated circuits (120) has an electrical interface (102,104,106), for providing electrical coupling to the IC (120) and a low-pass filter structure connected between the electric interface (102,104,106) and the IC (120). The low-pass filter structure comprises a first inductive element (108) connected in series with the electrical interface (102,104,106) for simulating wire bond reactances, a second inductive element (114) connected in series with the first inductive element (108) for making contact with the IC (120) and at least one capacitor (110,112) connected between ground and a point common to both the first (108) and the second (114) inductive elements, for providing shunt capacitance and defining a Tee type low-pass matched filter at the input (121) and the output (123) of the IC (120).
    Type: Grant
    Filed: December 2, 1991
    Date of Patent: May 10, 1994
    Assignee: Motorola, Inc.
    Inventors: Craig Fullerton, Douglas J. Mathews