Abstract: An I/O bus expansion interface is disclosed which enables an I/O device having an n-bit data bus to be interfaced to an m times n-bit I/O data bus of a host processor. This I/O bus expansion circuit maximizes the computer processor's performance by providing full I/O data bus bandwidth and allowing overlap of processor execution and I/O bus expansion interface circuit operation. This is accomplished by: (1) prefetching multiple control and/or data fields from the I/O device and presenting that information to the host without delay and (2) burst writing multiple fields from the host to the bus expansion interface circuit, without delay of the host, and thereafter making these fields individually available to the I/O device.