Patents by Inventor Craig Hansen

Craig Hansen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230089073
    Abstract: Provided herein are GLP-1 receptor modulator compounds, pharmaceutical compositions, methods of their preparation, and methods of their use in treatment, and/or diagnosis.
    Type: Application
    Filed: January 27, 2022
    Publication date: March 23, 2023
    Inventors: Xiaohui DU, Ray Fucini, Xu Ran, Chien-Hung Yeh, Xiang Zhou, Rui Gao, Joon Won Jeong, Li Liu, Subas Man Sakya, Xiaofang Wang, Hiroyuki Kawai, Craig Lee, David Lloyd, Stig Hansen
  • Patent number: 11443755
    Abstract: Systems and techniques for automated voice assistant personality selector are described herein. A task may be identified that is to be completed by a user of a voice-enabled virtual assistant. A response may be output in connection with the task using a default personality for the voice-enabled virtual assistant selected based on the task. A task completion checkpoint may be determined for the task. It may be identified that the task completion checkpoint has not been reached. A personality profile of the user may be compared to personality data of a set of voice-enabled virtual assistant profiles corresponding to respective members of a set of available voice personalities for the voice-enabled virtual assistant. An escalation personality may be selected for the voice-enabled virtual assistant based the comparison and the task. Commands for facilitating user completion of the task may be transmitted via the voice-enabled virtual assistant using the selected escalation personality.
    Type: Grant
    Filed: May 1, 2020
    Date of Patent: September 13, 2022
    Assignee: Wells Fargo Bank, N.A.
    Inventors: Nathan Craig Bricklin, Gregory John Hansen, Chris Theodore Kalaboukis, Adnan Khan, Kathleen E. McGinn, Ryan Benjamin Miller, Wairnola Marria Rhodriquez
  • Patent number: 10365926
    Abstract: A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width. The present invention provides operands which are substantially larger than the data path with of the processor by using the contents of a general purpose register to specify a memory address at which a plurality of data path widths of data can be read or written, as well as the size and shape of the operand. In addition, several instructions and apparatus for implementing these instructions are described which obtain performance advantages if the operands are not limited to the width and accessible number of general purpose registers.
    Type: Grant
    Filed: May 5, 2016
    Date of Patent: July 30, 2019
    Assignee: MicroUnity Systems Engineering, Inc.
    Inventors: Craig Hansen, John Moussouris, Alexia Massalin
  • Publication number: 20190065149
    Abstract: A processor and method for performing outer product and outer product accumulation operations on vector operands requiring large numbers of multiplies and accumulations is disclosed.
    Type: Application
    Filed: October 2, 2018
    Publication date: February 28, 2019
    Applicant: MicroUnity Systems Engineering, Inc.
    Inventors: Craig Hansen, John Moussouris, Alexia Massalin
  • Patent number: 10204055
    Abstract: Expandably wide operations are disclosed in which operands wider than the data path between a processor and memory are used in executing instructions. The expandably wide operands reduce the influence of the characteristics of the associated processor in the design of functional units performing calculations, including the width of the register file, the processor clock rate, the exception subsystem of the processor, and the sequence of operations in loading and use of the operand in a wide cache memory.
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: February 12, 2019
    Assignee: MicroUnity Systems Engineering, Inc.
    Inventors: Craig Hansen, John Moussouris, Alexia Massalin
  • Patent number: 10120649
    Abstract: A processor and method for performing outer product and outer product accumulation operations on vector operands requiring large numbers of multiplies and accumulations is disclosed.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: November 6, 2018
    Assignee: MicroUnity Systems Engineering, Inc.
    Inventors: Craig Hansen, John Moussouris, Alexia Massalin
  • Publication number: 20180173635
    Abstract: Expandably wide operations are disclosed in which operands wider than the data path between a processor and memory are used in executing instructions. The expandably wide operands reduce the influence of the characteristics of the associated processor in the design of functional units performing calculations, including the width of the register file, the processor clock rate, the exception subsystem of the processor, and the sequence of operations in loading and use of the operand in a wide cache memory.
    Type: Application
    Filed: September 7, 2017
    Publication date: June 21, 2018
    Applicant: MicroUnity Systems Engineering, Inc.
    Inventors: Craig Hansen, John Moussouris, Alexia Massalin
  • Publication number: 20180032312
    Abstract: A processor and method for performing outer product and outer product accumulation operations on vector operands requiring large numbers of multiplies and accumulations is disclosed.
    Type: Application
    Filed: July 29, 2016
    Publication date: February 1, 2018
    Inventors: Craig Hansen, John Moussouris, Alexia Massalin
  • Patent number: 9785565
    Abstract: Expandably wide operations are disclosed in which operands wider than the data path between a processor and memory are used in executing instructions. The expandably wide operands reduce the influence of the characteristics of the associated processor in the design of functional units performing calculations, including the width of the register file, the processor clock rate, the exception subsystem of the processor, and the sequence of operations in loading and use of the operand in a wide cache memory.
    Type: Grant
    Filed: June 25, 2015
    Date of Patent: October 10, 2017
    Assignee: MicroUnity Systems Engineering, Inc.
    Inventors: Craig Hansen, John Moussouris, Alexia Massalin
  • Publication number: 20160321071
    Abstract: A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width. The present invention provides operands which are substantially larger than the data path with of the processor by using the contents of a general purpose register to specify a memory address at which a plurality of data path widths of data can be read or written, as well as the size and shape of the operand. In addition, several instructions and apparatus for implementing these instructions are described which obtain performance advantages if the operands are not limited to the width and accessible number of general purpose registers.
    Type: Application
    Filed: May 5, 2016
    Publication date: November 3, 2016
    Inventors: Craig Hansen, John Moussouris, Alexia Massalin
  • Patent number: 9378018
    Abstract: A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width. The present invention provides operands which are substantially larger than the data path with of the processor by using the contents of a general purpose register to specify a memory address at which a plurality of data path widths of data can be read or written, as well as the size and shape of the operand. In addition, several instructions and apparatus for implementing these instructions are described which obtain performance advantages if the operands are not limited to the width and accessible number of general purpose registers.
    Type: Grant
    Filed: August 17, 2015
    Date of Patent: June 28, 2016
    Assignee: MicroUnity Systems Engineering, Inc.
    Inventors: Craig Hansen, John Moussouris, Alexia Massalin
  • Publication number: 20160048393
    Abstract: A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width. The present invention provides operands which are substantially larger than the data path with of the processor by using the contents of a general purpose register to specify a memory address at which a plurality of data path widths of data can be read or written, as well as the size and shape of the operand. In addition, several instructions and apparatus for implementing these instructions are described which obtain performance advantages if the operands are not limited to the width and accessible number of general purpose registers.
    Type: Application
    Filed: August 17, 2015
    Publication date: February 18, 2016
    Inventors: Craig Hansen, John Moussouris, Alexia Massalin
  • Patent number: 9229713
    Abstract: A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width. The present invention provides operands which are substantially larger than the data path width of the processor by using the contents of a general purpose register to specify a memory address at which a plurality of data path widths of data can be read or written, as well as the size and shape of the operand. In addition, several instructions and apparatus for implementing these instructions are described which obtain performance advantages if the operands are not limited to the width and accessible number of general purpose registers.
    Type: Grant
    Filed: August 22, 2012
    Date of Patent: January 5, 2016
    Assignee: MicroUnity Systems Engineering, Inc.
    Inventors: Craig Hansen, John Moussouris, Alexia Massalin
  • Publication number: 20150378734
    Abstract: Expandably wide operations are disclosed in which operands wider than the data path between a processor and memory are used in executing instructions. The expandably wide operands reduce the influence of the characteristics of the associated processor in the design of functional units performing calculations, including the width of the register file, the processor clock rate, the exception subsystem of the processor, and the sequence of operations in loading and use of the operand in a wide cache memory.
    Type: Application
    Filed: June 25, 2015
    Publication date: December 31, 2015
    Inventors: Craig Hansen, John Moussouris, Alexia Massalin
  • Patent number: 8943119
    Abstract: A system and a method are configured to improve the performance of general-purpose processors by implementing a functional unit that computes the product of a matrix operand with a vector operand, producing a vector result. The functional unit fully utilizes the entire resources of a 128 b by 128 b multiplier regardless of the operand size, as the number of elements of the matrix and vector operands increase as operand size is reduced. The unit performs both fixed-point and floating-point multiplications and additions with the highest-possible intermediate accuracy with modest resources.
    Type: Grant
    Filed: May 2, 2012
    Date of Patent: January 27, 2015
    Assignee: Microunity Systems Engineering, Inc.
    Inventors: Craig Hansen, Bruce Bateman, John Moussouris
  • Publication number: 20140351565
    Abstract: Systems and apparatuses are presented relating a programmable processor comprising an execution unit that is operable to decode and execute instructions received from an instruction path and partition data stored in registers in the register file into multiple data elements, the execution unit capable of executing group data handling operations that re-arrange data elements in different ways in response to data handling instructions, the execution unit further capable of executing a plurality of different group floating-point and group integer arithmetic operations that each arithmetically operates on the multiple data elements stored in registers in the register file to produce a catenated result that is returned to a register in the register file, wherein the catenated result comprises a plurality of individual results.
    Type: Application
    Filed: March 24, 2014
    Publication date: November 27, 2014
    Applicant: MICROUNITY SYSTEMS ENGINEERING, INC.
    Inventors: Craig HANSEN, John MOUSSOURIS, Alexia MASSALIN
  • Patent number: 8812821
    Abstract: A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width. The present invention provides operands which are substantially larger than the data path width of the processor by using the contents of a general purpose register to specify a memory address at which a plurality of data path widths of data can be read or written, as well as the size and shape of the operand. In addition, several instructions and apparatus for implementing these instructions are described which obtain performance advantages if the operands are not limited to the width and accessible number of general purpose registers.
    Type: Grant
    Filed: August 13, 2012
    Date of Patent: August 19, 2014
    Assignee: MicroUnity Systems Engineering, Inc.
    Inventors: Craig Hansen, John Moussouris, Alexia Massalin
  • Patent number: 8769248
    Abstract: Systems and apparatuses are presented relating a programmable processor comprising an execution unit that is operable to decode and execute instructions received from an instruction path and partition data stored in registers in the register file into multiple data elements, the execution unit capable of executing group data handling operations that re-arrange data elements in different ways in response to data handling instructions, the execution unit further capable of executing a plurality of different group floating-point and group integer arithmetic operations that each arithmetically operates on the multiple data elements stored in registers in the register file to produce a catenated result that is returned to a register in the register file, wherein the catenated result comprises a plurality of individual results.
    Type: Grant
    Filed: June 11, 2012
    Date of Patent: July 1, 2014
    Assignee: Microunity Systems Engineering, Inc.
    Inventors: Craig Hansen, John Moussouris, Alexia Massalin
  • Patent number: 8727642
    Abstract: There is provided a quick-release camera mounting system for connecting a camera to an object, such as tripod, backpack strap or belt. The camera has a base. The system includes an adapter with a base that is connectable to the object. The adapter has a protrusion that operatively connects to and extends outwards from its base. The system includes a camera mount threadably connecting to the base of the camera and for connecting with the adapter. The camera mount has a locking mechanism capable of quickly releasing the adapter from the camera mount. The locking mechanism includes a centrally disposed recessed portion. The protrusion of the adapter is shaped to fit within the recessed portion and engage with the locking mechanism for selectively connecting the adapter to the camera mount.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: May 20, 2014
    Inventors: Wilson Tse, Craig Hansen
  • Patent number: 8683182
    Abstract: Systems and apparatuses are presented relating a programmable processor comprising an execution unit that is operable to decode and execute instructions received from an instruction path and partition data stored in registers in the register file into multiple data elements, the execution unit capable of executing group data handling operations that re-arrange data elements in different ways in response to data handling instructions, the execution unit further capable of executing a plurality of different group floating-point and group integer arithmetic operations that each arithmetically operates on the multiple data elements stored in registers in the register file to produce a catenated result that is returned to a register in the register file, wherein the catenated result comprises a plurality of individual results.
    Type: Grant
    Filed: June 11, 2012
    Date of Patent: March 25, 2014
    Assignee: Microunity Systems Engineering, Inc.
    Inventors: Craig Hansen, John Moussouris, Alexia Massalin