Patents by Inventor Craig Hansen
Craig Hansen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20040156248Abstract: A programmable processor and method for improving the performance of processors by incorporating an execution unit operable to decode and execute single instructions in an instruction set comprising (a) group instructions that operate on a plurality of data elements in partitioned fields of a register to produce a catenated result, (b) aligned memory operations that move data between memory and register where the memory operand is aligned, and (c) unaligned memory operations where the memory operand is unaligned.Type: ApplicationFiled: November 20, 2003Publication date: August 12, 2004Applicant: MICROUNITY SYSTEMS ENGINEERING, INC.Inventors: Craig Hansen, John Moussouris
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Publication number: 20040158689Abstract: A system and software for improving the performance of processors by incorporating an execution unit operable to decode and execute single instructions in an instruction set comprising (a) group instructions that operate on a plurality of data elements in partitioned fields of a register to produce a catenated result, (b) aligned memory operations that move data between memory and register where the memory operand is aligned, and (c) unaligned memory operations where the memory operand is unaligned.Type: ApplicationFiled: November 20, 2003Publication date: August 12, 2004Applicant: MICROUNITY SYSTEMS ENGINEERING, INC.Inventors: Craig Hansen, John Moussouris
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Publication number: 20040153632Abstract: A system and software for improving the performance of processors by incorporating an execution unit operable to decode and execute single instructions specifying a data selection operand and a first and a second register providing a plurality of data elements, the data selection operand comprising a plurality of fields each selecting one of the plurality of data elements, the execution unit operable to provide the data element selected by each field of the data selection operand to a predetermined position in a catenated result.Type: ApplicationFiled: January 16, 2004Publication date: August 5, 2004Applicant: MICROUNITY SYSTEMS ENGINEERING, INC.Inventors: Craig Hansen, John Moussouris
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Publication number: 20040103266Abstract: A programmable processor and method for improving the performance of processors by incorporating an execution unit operable to decode and execute single instructions specifying both a shift amount and a register containing a plurality of data elements, wherein the execution unit is operable to shift a subfield of each of the plurality of data elements by the shift amount to produce a second plurality of data elements; and provide the second plurality of data elements as a catenated result.Type: ApplicationFiled: November 13, 2003Publication date: May 27, 2004Applicant: MICROUNITY SYSTEMS ENGINEERING, INC.Inventors: Craig Hansen, John Moussouris
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Publication number: 20040098567Abstract: A programmable processor and method for improving the performance of processors by incorporating an execution unit operable to decode and execute single instructions specifying both a shift amount and a register containing a plurality of data elements, wherein the execution unit is operable to shift a subfield of each of the plurality of data elements by the shift amount to produce a second plurality of data elements; and provide the second plurality of data elements as a catenated result.Type: ApplicationFiled: November 14, 2003Publication date: May 20, 2004Applicant: MICROUNITY SYSTEMS ENGINEERING, INC.Inventors: Craig Hansen, John Moussouris
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Publication number: 20040098548Abstract: A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width. The present invention provides operands which are substantially larger than the data path width of the processor by using the contents of a general purpose register to specify a memory address at which a plurality of data path widths of data can be read or written, as well as the size and shape of the operand. In addition, several instructions and apparatus for implementing these instructions are described which obtain performance advantages if the operands are not limited to the width and accessible number of general purpose registers.Type: ApplicationFiled: December 19, 2003Publication date: May 20, 2004Inventors: Craig Hansen, John Moussouris, Alexia Massalin
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Patent number: 6725356Abstract: The present invention provides a system and method for improving the performance of general purpose processors by expanding at least one source operand to a width greater than the width of either the general purpose register or the data path width. In addition, the present invention provides several classes of instructions which cannot be performed efficiently if the operands are limited to the width and accessible number of general purpose registers. The present invention provides operands which are substantially larger than the data path width of the processor by using a general purpose register to specify a memory address from which at least more than one, but typically several data path widths of data can be read. The present invention also provides for the efficient usage of a multiplier array that is fully used for high precision arithmetic, but is only partly used for other, lower precision operations.Type: GrantFiled: August 2, 2001Date of Patent: April 20, 2004Assignee: MicroUnity Systems Engineering, Inc.Inventors: Craig Hansen, John Moussouris
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Publication number: 20040049663Abstract: The present invention provides a system and method for expanding at least one source operand to a width greater than the width of either the general purpose register or the data path width. Operands are provided which are substantially larger than the data path width of the processor. A general purpose register is used to specify a memory address from which at least more than one, but typically several data path widths of data can be read. The data path functional unit is augmented with dedicated storage to which the memory operand is copied on an initial execution of the instruction. Further execution of the instruction or other similar instructions that specify the same memory address can read the dedicated storage to obtain the operand value. However, such reads are subject to conditions to verify that the memory operand has not been altered by intervening instructions.Type: ApplicationFiled: May 13, 2003Publication date: March 11, 2004Applicant: MICROUNITY SYSTEMS ENGINEERING, INC.Inventors: Craig Hansen, John Moussouris
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Patent number: 6643765Abstract: A programmable processor that comprises a general purpose processor architecture, capable of operation independent of another host processor, having a virtual memory addressing unit, an instruction path and a data path; an external interface; a cache operable to retain data communicated between the external interface and the data path; at least one register file configurable to receive and store data from the data path and to communicate the stored data to the data path; and a multi-precision execution unit coupled to the data path. The multi-precision execution unit is configurable to dynamically partition data received from the data path to account for an elemental width of the data and is capable of performing group floating-point operations on multiple operands in partitioned fields of operand registers and returning catenated results. In other embodiments the multi-precision execution unit is additionally configurable to execute group integer and/or group data handling operations.Type: GrantFiled: March 24, 2000Date of Patent: November 4, 2003Assignee: Microunity Systems Engineering, Inc.Inventors: Craig Hansen, John Moussouris
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Publication number: 20030110197Abstract: The present invention provides a system and method for improving the performance of general-purpose processors by implementing a functional unit that computes the product of a matrix operand with a vector operand, producing a vector result. The functional unit fully utilizes the entire resources of a 128b by 128b multiplier regardless of the operand size, as the number of elements of the matrix and vector operands increase as operand size is reduced. The unit performs both fixed-point and floating-point multiplications and additions with the highest-possible intermediate accuracy with modest resources.Type: ApplicationFiled: September 4, 2002Publication date: June 12, 2003Inventors: Craig Hansen, Bruce Bateman, John Moussouris
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Publication number: 20020133682Abstract: The present invention provides a system and method for improving the performance of general purpose processors by expanding at least one source operand to a width greater than the width of either the general purpose register or the data path width. In addition, the present invention provides several classes of instructions which cannot be performed efficiently if the operands are limited to the width and accessible number of general purpose registers The present invention provides operands which are substantially larger than the data path width of the processor by using a general purpose register to specify a memory address from which at least moire than one, but typically several data path widths of data can be read. The present invention also provides for the efficient usage of a multiplier array that is fully used for high precision arithmetic, but is only partly used for other, lower precision operations.Type: ApplicationFiled: August 2, 2001Publication date: September 19, 2002Inventors: Craig Hansen, John Moussouris
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Patent number: 6378060Abstract: The present invention provides a cross-bar circuit that implements a switch of a broadband processor. In an exemplary embodiment, the present invention provides a cross-bar circuit that, in response to partially-decoded instruction information and in response to datapath information, (1) allows any bit from a 2n-bit (e.g. 256-bit) input source word to be switched into any bit position of a 2m-bit (e.g. 128-bit) output destination word and (2) provides the ability to set-to-zero any bit in said 2m-bit output destination word. The cross-bar circuit includes: (1) a switch circuit which includes 2m 2n:1 multiplexor circuits, where each of the 2n:1 multiplexor circuits (a) has a unique n-bit (e.g.Type: GrantFiled: February 11, 2000Date of Patent: April 23, 2002Assignee: Microunity Systems Engineering, Inc.Inventors: Craig Hansen, Bruce Bateman, John Moussouris
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Patent number: 6295599Abstract: The present invention provides a system and method for improving the performance of general purpose processors by expanding at least one source operand to a width greater than the width of either the general purpose register or the data path width. In addition, the present invention provides several classes of instructions which cannot be performed efficiently if the operands are limited to the width and accessible number of general purpose registers. The present invention provides operands which are substantially larger than the data path width of the processor by using a general purpose register to specify a memory address from which at least more than one, but typically several data path widths of data can be read. The present invention also provides for the efficient usage of a multiplier array that is fully used for high precision arithmetic, but is only partly used for other, lower precision operations.Type: GrantFiled: August 24, 1999Date of Patent: September 25, 2001Assignee: MicroUnity Systems EngineeringInventors: Craig Hansen, John Moussouris
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Patent number: 5822603Abstract: A general purpose, programmable media processor for processing and transmitting a media data stream of audio, video, radio, graphics, encryption, authentication, and networking information in real-time. The media processor incorporates an execution unit that maintains substantially peak data throughout of media data streams. The execution unit includes a dynamically partionable multi-precision arithmetic unit, programmable switch and programmable extended mathematical element. A high bandwidth external interface supplies media data streams at substantially peak rates to a general purpose register file and the multi-precision execution unit. A memory management unit, and instruction and data cache/buffers are also provided. High bandwidth memory controllers are linked in series to provide a memory channel to the general purpose, programmable media processor.Type: GrantFiled: November 22, 1996Date of Patent: October 13, 1998Assignee: Microunity Systems Engineering, Inc.Inventors: Craig Hansen, John Moussouris
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Patent number: 5809321Abstract: A general purpose, programmable media processor for processing and transmitting a media data stream of audio, video, radio, graphics, encryption, authentication, and networking information in real-time. The media processor incorporates an execution unit that maintains substantially peak data throughout of media data streams. The execution unit includes a dynamically partionable multi-precision arithmetic unit, programmable switch and programmable extended mathematical element. A high bandwidth external interface supplies media data streams at substantially peak rates to a general purpose register file and the multi-precision execution unit. A memory management unit, and instruction and data cache/buffers are also provided. High bandwidth memory controllers are linked in series to provide a memory channel to the general purpose, programmable media processor.Type: GrantFiled: November 22, 1996Date of Patent: September 15, 1998Assignee: MicroUnity Systems Engineering, Inc.Inventors: Craig Hansen, John Moussouris
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Patent number: 5794060Abstract: A general purpose, programmable media processor for processing and transmitting a media data stream of audio, video, radio, graphics, encryption, authentication, and networking information in real-time. The media processor incorporates an execution unit that maintains substantially peak data throughout of media data streams. The execution unit includes a dynamically partionable multi-precision arithmetic unit, programmable switch and programmable extended mathematical element. A high bandwidth external interface supplies media data streams at substantially peak rates to a general purpose register file and the multi-precision execution unit. A memory management unit, and instruction and data cache/buffers are also provided. High bandwidth memory controllers are linked in series to provide a memory channel to the general purpose, programmable media processor.Type: GrantFiled: November 22, 1996Date of Patent: August 11, 1998Assignee: Microunity Systems Engineering, Inc.Inventors: Craig Hansen, John Moussouris
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Patent number: 5794061Abstract: A general purpose, programmable media processor for processing and transmitting a media data stream of audio, video, radio, graphics, encryption, authentication, and networking information in real-time. The media processor incorporates an execution unit that maintains substantially peak data throughout of media data streams. The execution unit includes a dynamically partionable multi-precision arithmetic unit, programmable switch and programmable extended mathematical element. A high bandwidth external interface supplies media data streams at substantially peak rates to a general purpose register file and the multi-precision execution unit. A memory management unit, and instruction and data cache/buffers are also provided. High bandwidth memory controllers are linked in series to provide a memory channel to the general purpose, programmable media processor.Type: GrantFiled: November 22, 1996Date of Patent: August 11, 1998Assignee: Microunity Systems Engineering, Inc.Inventors: Craig Hansen, John Moussouris
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Patent number: 5742840Abstract: A general purpose, programmable media processor for processing and transmitting a media data stream of audio, video, radio, graphics, encryption, authentication, and networking information in real-time. The media processor incorporates an execution unit that maintains substantially peak data throughout of media data streams. The execution unit includes a dynamically partionable multi-precision arithmetic unit, programmable switch and programmable extended mathematical element. A high bandwidth external interface supplies media data streams at substantially peak rates to a general purpose register file and the multi-precision execution unit. A memory management unit, and instruction and data cache/buffers are also provided. High bandwidth memory controllers are linked in series to provide a memory channel to the general purpose, programmable media processor.Type: GrantFiled: August 16, 1995Date of Patent: April 21, 1998Assignee: Microunity Systems Engineering, Inc.Inventors: Craig Hansen, John Moussouris
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Patent number: D355551Type: GrantFiled: July 12, 1993Date of Patent: February 21, 1995Assignee: Minnesota American, Inc.Inventors: George E. McNamara, Craig Hansen