Abstract: A fractional-N synthesized chirp generator includes a fractional-N synthesizer and a digital ramp synthesizer. The fractional-N synthesizer has a frequency synthesizer and a sigma-delta modulator module. The fractional-N synthesizer is configured to receive a reference frequency input signal and a frequency control value. The fractional-N synthesizer is configured to transform the reference frequency signal and the frequency control value to a chirped radio frequency (RF) output signal in a deterministic manner. The digital ramp synthesizer is configured to receive the reference frequency input signal and configured to generate the frequency control value utilizing the reference frequency input signal. The digital ramp synthesizer is further configured to provide the frequency control value to the fractional-N synthesizer. The frequency control value varies with time.

Abstract: Examples of a system and method for sigma-delta analog-to-digital conversion of an electrical input signal are disclosed. A bandpass-filtered signal based on an electrical input signal and an analog feedback signal may be provided. A multi-bit digital representation of the bandpass-filtered signal may be provided. An analog representation of the multi-bit digital representation may be provided. A return-to-zero (RTZ) carving operation may be performed on the analog representation to obtain the analog feedback signal.

Abstract: An example of a radio frequency (RF) receiver system for communication may include a receive channel frequency converter configured to provide a second receive calibration signal during a receive calibration mode based on a first receive calibration signal and a receive reference signal. The system may include a receive pre-distortion module coupled to the receive channel frequency converter. The receive pre-distortion module may be configured to provide a fourth receive calibration signal during the receive calibration mode based on a third receive calibration signal and one or more receive calibration adjustment signals. The one or more receive calibration adjustment signals may comprise an offset parameter associated with DC offset and an imbalance parameter associated with at least one of gain and phase imbalances.

Abstract: An example of a radio frequency (RF) transmitter system for communication may include a transmit pre-distortion module configured to provide a second transmit calibration signal during a transmit calibration mode based on a first transmit calibration signal and one or more transmit calibration adjustment signals. The one or more transmit calibration adjustment signals may include an offset parameter associated with DC offset and an imbalance parameter associated with at least one of gain and phase imbalances. The system may include a transmit channel frequency converter coupled to the transmit pre-distortion module. The transmit channel frequency converter may be configured to provide a fourth transmit calibration signal during the transmit calibration mode based on a third transmit calibration signal and a transmit reference signal.

Abstract: A radio frequency transceiver for off-line transmit and receive calibrations includes: a transmit pre-distortion module configured to receive a transmit calibration signal during a transmit calibration mode, a transmit communication signal during a transmit communication operation mode, and one or more transmit calibration adjustment signals; a transmit channel frequency converter; and a transmit calibration module configured to provide the one or more transmit calibration adjustment signals and the transmit calibration signal to the transmit pre-distortion module.

Abstract: A communication system includes a multiplexer configured to multiplex a first set of data channels into a first data channel and to multiplex a second set of data channels into a second data channel, and a delay adjuster configured to adjustably delay the first data channel based on a delay adjust command. The communication system also includes a first amplifier configured to amplify the delayed first channel into a first output data channel, and a second amplifier configured to amplify the second data channel into a second output data channel. The communication system further includes a first driver configured to convert the first output data channel into a first drive signal to drive an optical modulator, and a second driver configured to convert the second output data channel into a second drive signal to drive the optical modulator.

Abstract: A fractional-N synthesized chirp generator includes a fractional-N synthesizer and a digital ramp synthesizer. The fractional-N synthesizer has a frequency synthesizer and a sigma-delta modulator module. The fractional-N synthesizer is configured to receive a reference frequency input signal and a frequency control value. The fractional-N synthesizer is configured to transform the reference frequency signal and the frequency control value to a chirped radio frequency (RF) output signal in a deterministic manner. The digital ramp synthesizer is configured to receive the reference frequency input signal and configured to generate the frequency control value utilizing the reference frequency input signal. The digital ramp synthesizer is further configured to provide the frequency control value to the fractional-N synthesizer. The frequency control value varies with time.

Abstract: High-speed, high-performance, low-power transponders, serializers and deserializers are disclosed. A transponder may include a transmitter and a receiver. A serializer may include (i) a serdes framer interface (SFI) circuit for receiving data channels and a reference channel from a framer and realigning the data channels, (ii) a clock multiplier unit (CMU) for receiving a clock frequency and translating the clock frequency to a higher clock frequency, (iii) a multiplexing circuit for merging data channels into one data channel, (iv) an output driver stage, (v) a reference selection circuit for selecting a reference clock, filtering the reference clock, and providing to the CMU one of the selected reference clock or a filtered reference clock.

Abstract: A radio frequency transceiver for off-line transmit and receive calibrations includes: a transmit pre-distortion module configured to receive a transmit calibration signal during a transmit calibration mode, a transmit communication signal during a transmit communication operation mode, and one or more transmit calibration adjustment signals; a transmit channel frequency converter; and a transmit calibration module configured to provide the one or more transmit calibration adjustment signals and the transmit calibration signal to the transmit pre-distortion module.

Abstract: An integrated circuit includes a serdes framer interface (SFI) circuit for receiving a first set of data channels and a reference channel, generating first logic levels for the first set of data channels, and realigning the first set of data channels relative to a reference channel. The integrated circuit further includes a multiplexing circuit for receiving a second set of data channels and for merging the second set of data channels into one or more data channels. The second set of data channels is generated based on the first set of data channels. A data rate of the one or more data channels is higher than a data rate of the second set of data channels.

Abstract: A communication system includes a front-end multi-throw switch, a back-end multi-throw switch, multiple filters and a switch controller. The front-end multi-throw switch includes front-end throws and a front-end pole. The front-end pole is coupled to a receive channel or a transmit channel. The front-end pole is switchably coupled to one of the front-end throws. The back-end multi-throw switch includes back-end throws and a back-end pole. Each of the back-end throws is associated with a corresponding one of the front-end throws. The back-end pole is coupled to the receive channel or the transmit channel. The back-end pole is switchably coupled to one of the back-end throws. The one of the back-end throws corresponds to the one of the front-end throws. The filters are interposed between the front-end multi-throw switch and the back-end multi-throw switch. Each of the filters has a first port coupled to one of the front-end throws and a second port coupled to one of the back-end throws.

Abstract: A communication system includes a front-end multi-throw switch, a back-end multi-throw switch, multiple filters and a switch controller. The front-end multi-throw switch includes front-end throws and a front-end pole. The front-end pole is coupled to a receive channel or a transmit channel. The front-end pole is switchably coupled to one of the front-end throws. The back-end multi-throw switch includes back-end throws and a back-end pole. Each of the back-end throws is associated with a corresponding one of the front-end throws. The back-end pole is coupled to the receive channel or the transmit channel. The back-end pole is switchably coupled to one of the back-end throws. The one of the back-end throws corresponds to the one of the front-end throws. The filters are interposed between the front-end multi-throw switch and the back-end multi-throw switch. Each of the filters has a first port coupled to one of the front-end throws and a second port coupled to one of the back-end throws.

Abstract: A multi-channel filtering system for use with a transceiver includes a front-end multi-pole, multi-throw switch, a back-end multi-pole, multi-throw switch, and a plurality of filters. The front-end switch includes a receive pole, a transmit pole, and a plurality of switch throws. The back-end switch also includes a receive pole, a transmit pole, and a plurality of switch throws. Each of the plurality of filters has first and second ports, each first port coupled to one of the switch throws of the front-end switch, and each second port coupled to one of the switch throws of the back-end switch. Using this configuration, filters of differing bandwidths can be switched in during signal reception and/or transmission, thereby tailoring the communication rate to the particular conditions.

Abstract: A multi-channel filtering system for use with a transceiver includes a front-end multi-pole, multi-throw switch, a back-end multi-pole, multi-throw switch, and a plurality of filters. The front-end switch includes a receive pole, a transmit pole, and a plurality of switch throws. The back-end switch also includes a receive pole, a transmit pole, and a plurality of switch throws. Each of the plurality of filters has first and second ports, each first port coupled to one of the switch throws of the front-end switch, and each second port coupled to one of the switch throws of the back-end switch. Using this configuration, filters of differing bandwidths can be switched in during signal reception and/or transmission, thereby tailoring the communication rate to the particular conditions.

Abstract: High-speed, high-performance, low-power transponders, serializers and deserializers are disclosed. A transponder may include a transmitter and a receiver. A serializer may include (i) a serdes framer interface (SFI) circuit for receiving data channels and a reference channel from a framer and realigning the data channels, (ii) a clock multiplier unit (CMU) for receiving a clock frequency and translating the clock frequency to a higher-clock frequency, (iii) a multiplexing circuit for merging data channels into one data channel, (iv) an output driver stage, (v) a reference selection circuit for selecting a reference clock, filtering the reference clock, and providing to the CMU one of the selected reference clock or a filtered reference clock.

Abstract: A multidetector (40) circuit for use in a plurality of carrier recovery systems (10, 70) for recovery for a suppressed carrier modulated signal. The multidetector (40) receives demodulated, in-phase x and quadrature phase y components of a baseband signal (sn(t)) and generates output signals for use in a plurality of carrier recovery systems (10, 70). The multidetector (40) generates a lock detection signal that varies primarily in accordance with a lock signal x2y2 and a fourth-order amplitude detection signal (x2+y2)2 for use in either system. The multidetector particularly generates a phase error signal xy(x2−y2) for use in a Costas carrier recovery system (10). The multidetector also generates a second-order amplitude detection signal (x2+y2) for use in either system which can be used to adjust the amplitude of the incoming, modulated signal in order to control the loop gain of the carrier recovery phase locked loop.

Abstract: Methods and devices for predistorted 12/4 Quadrature Amplitude Modulation that compensate for distortion from a nonlinear element. Modulator input bits are mapped (40) to a plurality of nonreturn-to-zero (NRZ) modulator control bit (20-30). The mapping is determined by desired points on a 12/4 QAM constellation. At least one phase shift device (4, 6) receives an input signal and at least one of the plurality of modulator control bit. At least two quaternary phase shift keying (QPSK) devices (8, 10) receive phase shifted signals from at least one phase shift device. Each of at least two QPSK devices receives at least one of the plurality of NRZ symbols. An attenuator (32) that attenuates a first QPSK signal outputted from a first QPSK device of the at least two QPSK devices. A summer (34) sums the attenuated first QPSK signal with a second QPSK signal. The second QPSK signal is outputted from a second QPSK device of the two QPSK devices. The summer outputs a predistorted 12/4-QAM signal.

Abstract: A 2N-QAM macrocell for generating constellations with 2N symbols, where N is the number of bits in the digital data word [D0:DN−1] applied to the macrocell. Since the digital data word is applied directly to the macrocell, the need for a digital mapping chip is thus eliminated thus reducing the complexity and power consumption of the circuit. An important aspect of the invention is that the 2N-QAM macrocell is amenable to being fabricated as a single microwave monolithic integrated circuit (MMIC) or integrated circuit (IC). As such, a QAM circuit can be formed from two MMICs; the 2N-QAM macrocell and a quadrature hybrid phase shifting device formed on separate MMIC to form a 2N-QAM circuit or one MMIC containing both the 0/90 degree phase shifter and the 2N-QAM circuit. The phase shifting device is used to provide the in-phase and quadrature phase components of the local oscillator signal.