Abstract: The same basic ROM circuit may be used to provide memories of increased capacity for pre-existing systems having different fixed numbers of address inputs. The appropriate page configuration is selected to accommodate the number of address inputs in the system. The system is adapted to generate a page address signal having the required number of bits on the data bus. The selected page configuration is obtained by mask programming the address decoder and input buffer circuits. The page address signal from the data bus is routed through the data transfer buffers and stored in a RAM for use in conjunction with the row and column address inputs.