Abstract: The present invention induces provides a gettering trench on the front surface of a device substrate. In one embodiment it induces stress and simultaneously forms a gettering zone 40 for gettering impurities in an integrated circuit structure. In another embodiment, the trench is filled with gettering material 72 such as polysilicon. The two gettering mechanisms may be combined 82,84. The invention is useful for providing gettering in bonded wafers and in silicon-on-insulator devices (FIGS. 4,5).

Abstract: The present invention induces provides a gettering trench on the front surface of a device substrate. In one embodiment it induces stress and simultaneously forms a gettering zone 40 for gettering impurities in an integrated circuit structure. In another embodiment, the trench is filled with gettering material 72 such as polysilicon. The two gettering mechanisms may be combined 82,84. The invention is useful for providing gettering in bonded wafers and in silicon-on-insulator devices (FIGS. 4,5).

Abstract: Oxygen induced lattice slip defects are reduced in device layer 26 of silicon-on-insulator structure 12, 16, 26. At the bottom of trenches 22 notches 28 are etched into the dielectric layer 16. A thermal oxide process provides protrusions 30 of oxide into the substrate. The protrusions 30 direct defects into the support layer 12.

Abstract: A silicon on insulator substrate 8 provides islands of silicon 18 of uniform thickness by using a trench etch process and a silicon nitride layer 20 to provide a thickness control and polish stop for the silicon islands 18.

Abstract: A bonding method including pressing a pair of slices together with a liquid oxidant therebetween and subjecting the pair of slices to a temperature to bond the slices together. Preferably a liquid oxidant is applied to one of the slices before they are pressed together and then dried. The heating step for bonding is carried out at a sufficiently high temperature of at least 1100.degree. C. to make the slices pliable so as to comply with each other during the bonding step.

Abstract: A bonding method including pressing a pair of slices together with a liquid oxidant therebetween and subjecting the pair of slices to a temperature to bond the slices together. Preferably a liquid oxidant is applied to one of the slices before they are pressed together and then dried. The heating step for bonding is carried out at a sufficiently high temperature of at least 1100.degree. C. to make the slices pliable so as to comply with each other during the bonding step.

Abstract: A process including forming peaks and valleys in a bonding surface of a first wafer so that the peaks are at the scribe lines which define dice. The peaks and not the valleys of the first wafer is bonded to a bonding surface of a second wafer. The device forming steps are performed on one of the wafers. Finally, the wafer in which the devices are formed is cut through at the peaks to form the dice. The peaks may be substantially the size of the kerf produced by the cutting such that the dice are separated from the other wafer by the cutting step. Alternately, the peaks may have a width greater than the kerf produced by the cutting and remain attached to the other wafer by the remaining peak portions. The dice are then separated from the other wafer at the remaining peak portions by an additional step.

Abstract: Integrated circuits are formed by bonding two substrates together on a moat or recess. If the moat is exposed at a side wall, an optical fiber is inserted therein and communicates optically with a photoelectric device in the substrate by a slant side wall of the moat. If the moat is sealed by a cover layer resulting from removing all or most of the top substrate leaving the bonding layer as a cover, a pressure responsive device is formed on the cover layer directly or in the remaining top substrate over the sealed cavity.

Abstract: Integrated circuits are formed by bonding two substrates together on a moat or recess. If the moat is exposed at a side wall, an optical fiber is inserted therein and communicates optically with a photoelectric device in the substrate by a slant side wall of the moat. If the moat is sealed by a cover layer resulting from removing all or most of the top substrate leaving the bonding layer as a cover, a pressure responsive device is formed on the cover layer directly or in the remaining top substrate over the sealed cavity.

Abstract: A process including bonding a first device wafer to a handle wafer by an intermediate bonding oxide layer and thinning the device wafer to not greater than 7 mils. An epitaxial device layer of under 1 mil may be added. Device formation steps are performed on a first surface of the first device wafer. This is followed by removing the handle wafer to produce a resulting wafer having substantially the thickness of the first device layer. To produce a silicon on insulator (SOI), a third device wafer is bonded to the first surface of the first device wafer by the intermediate oxide layer and the third wafer is thinned to not greater than 40 microns. The first and third device wafers form the resulting SOI wafer.

Abstract: A method including forming an alignment moat of a first depth on a first surface of a substrate and performing all backside processing, forming a first oxide layer on the first surface and oxide bonding it to a handling wafer by oxide bonding. The substrate is then thinned from a second surface opposite the first surface down to a thickness less than the depth of the alignment moat so the alignment moat is exposed at a third surface for front side processing.

Abstract: Integrated circuits are formed by bonding two substrates together on a moat or recess. If the moat is exposed at a side wall, an optical fiber is inserted therein and communicates optically with a photoelectric device in the substrate by a slant side wall of the moat. If the moat is sealed by a cover layer resulting from removing all or most of the top substrate leaving the bonding layer as a cover, a pressure responsive device is formed on the cover layer directly or in the remaining top substrate over the sealed cavity.

Abstract: Plane indicating moats are formed extending through an epitaxial layer into a substrate simultaneous with the formation of the isolation moats which terminate within the epitaxial layer. The substrate is ground to a predetermined thickness after formation of the dielectric isolation and support structure. The composite structure is inserted in an etchant with conditions set to electrochemically etch only the substrate. The exposed plane indicating moats are used as a reference for a final polishing step.