Abstract: A method for a redundancy mechanism to increase defect and fault tolerance in semiconductor memories, such as DRAM, is disclosed. The repair of single cell, row, column or cluster faults is achieved by accessing a list of faulty regions in parallel with the main memory. This list of faulty regions uses a three-state storage device to allow groups of faulty memory locations to be marked with a single entry. This mechanism is designed to be fully transparent to the semiconductor memory, allowing full regular operation, no reduction in frequency, increase in area over conventional row and column redundancy or extra fabrication steps.