Abstract: Systems and methods for verifying Basic Input/Output System (BIOS) boot block code are described. In some embodiments, an Information Handling System (IHS) may include: a processor; a memory coupled to the processor, the memory comprising BIOS instructions stored thereon; and an embedded controller (EC) coupled to the memory, the EC configured to: after a power-on sequence of the IHS is initiated and before a power rail of the processor is turned on, unlock write access to the memory; perform an Error Correction Code (ECC) evaluation of a BIOS boot block code portion of the BIOS instructions; verify integrity of the BIOS boot block code portion; lock write access to the memory; and allow the processor to execute the BIOS instructions.

Abstract: In accordance with these and other embodiments of the present disclosure, a method may include determining whether a system management interrupt is expected to take more than a predetermined threshold duration to complete, determining whether audio data is actively streaming from a processor of an information handling system to an audio controller communicatively coupled to the processor and configured to process audio data communicated from the processor to the audio controller for reproduction to a speaker communicatively coupled to the audio controller, and executing the system management interrupt if the system management interrupt is expected to take less than a predetermined threshold duration to complete or if audio data is not actively streaming from the processor to the audio controller.

Abstract: In one or more embodiments, one or more systems, methods, and/or processes may determine, via a first switch, that a signal from an embedded controller has not been received; may determine if a second switch is actuated by a user; if the second switch is actuated, may display first information that indicates that power from the at least one of an external power source and a battery power source is received; may determine, via a third switch, if the at least one of the external power source and the battery power source includes the external power source; and if the at least one of the external power source and the battery power source includes the external power source, may display second information that indicates the at least one of the external power source and the battery power source includes the external power source.

Abstract: In one or more embodiments, one or more methods, processes and/or systems may receive multiple characters (e.g., a string), determine multiple offsets respectively corresponding to the multiple characters, determine multiple addresses based on a base address and the multiple offsets respectively corresponding to the multiple characters, and execute multiple subroutine call instructions to each of the multiple addresses. In one or more embodiments, an execution log of the subroutine call instructions to each of the multiple addresses may be analyzed. For instance, the execution log of the subroutine call instructions to each of the multiple addresses may be utilized in determining the multiple characters (e.g., the string) that were received. In one or more embodiments, determining the multiple characters may include determining offsets from a base address and utilizing the offsets as a mapping to characters. For example, the string may be recovered and/or recreated from the offsets.

Abstract: In one or more embodiments, one or more methods, processes and/or systems may receive multiple characters (e.g., a string), determine multiple offsets respectively corresponding to the multiple characters, determine multiple addresses based on a base address and the multiple offsets respectively corresponding to the multiple characters, and execute multiple subroutine call instructions to each of the multiple addresses. In one or more embodiments, an execution log of the subroutine call instructions to each of the multiple addresses may be analyzed. For instance, the execution log of the subroutine call instructions to each of the multiple addresses may be utilized in determining the multiple characters (e.g., the string) that were received. In one or more embodiments, determining the multiple characters may include determining offsets from a base address and utilizing the offsets as a mapping to characters. For example, the string may be recovered and/or recreated from the offsets.

Abstract: A method for automatic correction of nonvolatile memory in information handling systems includes storing ECC data for a compressed BIOS firmware. The ECC data are used to identify and correct error bits in the compressed BIOS firmware. The discovered error bits are recorded in the nonvolatile memory and accessed for a faster correction method for the compressed BIOS firmware than using the ECC data on subsequent attempts.

Abstract: In accordance with these and other embodiments of the present disclosure, a method may include determining whether a system management interrupt is expected to take more than a predetermined threshold duration to complete, determining whether audio data is actively streaming from a processor of an information handling system to an audio controller communicatively coupled to the processor and configured to process audio data communicated from the processor to the audio controller for reproduction to a speaker communicatively coupled to the audio controller, and executing the system management interrupt if the system management interrupt is expected to take less than a predetermined threshold duration to complete or if audio data is not actively streaming from the processor to the audio controller.

Abstract: A method for automatic correction of nonvolatile memory in information handling systems includes storing ECC data for a compressed BIOS firmware. The ECC data are used to identify and correct error bits in the compressed BIOS firmware. The discovered error bits may be recorded in the nonvolatile memory and accessed for a faster correction method for the compressed BIOS firmware than using the ECC data on subsequent attempts.

Abstract: In an information handling system (IHS), providing an IHS boot includes forcing the IHS to power on or reboot, retrieving a virtual serial peripheral interface (SPI) boot image using a virtual SPI bus, booting the IHS to the virtual SPI boot image, turning off the virtual SPI boot image, and updating a real SPI boot image.

Abstract: For reducing wake latency time of an information handling system (IHS), a non-volatile random access memory (NVRAM) of the IHS is updated every time a main random access memory (RAM) of the IHS is changed or refreshed, thereby saving memory data. In response to a sleep event, the IHS is transitioned from a higher activity state to a sleep state, thereby removing power provided to the RAM. In response to a resume event, the IHS is restored back to the higher activity state from the sleep state. Upon restoring the power to the RAM, contents of the NVRAM are copied to the RAM to restore the memory data in a virtually instant manner.

Abstract: In an information handling system (IHS), providing an IHS boot includes forcing the IHS to power on or reboot, retrieving a virtual serial peripheral interface (SPI) boot image using a virtual SPI bus, booting the IHS to the virtual SPI boot image, turning off the virtual SPI boot image, and updating a real SPI boot image.

Abstract: For reducing wake latency time of an information handling system (IHS), a non-volatile random access memory (NVRAM) of the IHS is updated every time a main random access memory (RAM) of the IHS is changed or refreshed, thereby saving memory data. In response to a sleep event, the IHS is transitioned from a higher activity state to a sleep state, thereby removing power provided to the RAM. In response to a resume event, the IHS is restored back to the higher activity state from the sleep state. Upon restoring the power to the RAM, contents of the NVRAM are copied to the RAM to restore the memory data in a virtually instant manner.