Abstract: A matrixed memory array device is disclosed that includes input ports and output ports. Each input port is coupled to a first data bus and each output port is coupled to a second data bus that is different and separate from the first data bus. A memory brick is placed at each cross-point between first data buses and second data buses so as to switchably couple frames of data from input ports to output ports. Each memory brick contains a plurality of eight transistor (8-T) memory cells that can be used to store, erase, read, write, and switchably couple a data bit from the input port to a corresponding output port.

Abstract: A matrixed memory array device is disclosed that includes input ports and output ports. Each input port is coupled to a first data bus and each output port is coupled to a second data bus that is different and separate from the first data bus. A memory brick is placed at each cross-point between first data buses and second data buses so as to switchably couple frames of data from input ports to output ports. Each memory brick contains a plurality of eight transistor (8-T) memory cells that can be used to store, erase, read, write, and switchably couple a data bit from the input port to a corresponding output port.

Abstract: A weighted round-robin scheduler includes a round-robin table that stores a plurality of cycle link lists. Each cycle link list includes a head flow identification (FLID) value identifying a first flow of the cycle link list, and a tail FLID value identifying a last flow of the cycle link list. A flow table is provided having a plurality of flow table entries. Each flow table entry is associated with a corresponding flow. Each flow table entry stores a parameter that identifies the weight assigned to the associated flow. A packet queue is associated with each flow table entry, wherein each packet queue is capable of storing a plurality of packets. The weighted round-robin scheduler also includes an idle cycle register having an idle cycle entry corresponding with each of the cycle link lists, wherein each idle cycle entry identifies the corresponding cycle link list as active or idle.