Abstract: A system for generating waveforms may include a memory configured to store a plurality of waveform segments, a plurality of waveform segment queues each coupled to receive waveform segments output by the memory, and a selection unit coupled to each of the waveform segment queues and configured to read waveform segments out of a selected one of the waveform segment queues. Each of the waveform segment queues may be configured to store a series of one or more waveform segments. The selection unit may be configured to access the first waveform segment queue during a first time period and to access the second waveform segment queue if a first trigger occurs.

Abstract: A Wide Area Serial PCI system for connecting peripheral devices to a computer. The WASP system includes a host computer system connected through a serial bus to a remote device. The serial bus can range from several meters to several kilometers or more. The host computer system includes a CPU and memory, and also includes a first Peripheral Component Interconnect (PCI) bus, also referred to as the local PCI bus. A primary bridge according to the present invention is coupled to the first PCI bus. The primary bridge includes PCI interface circuitry for interfacing to the first PCI bus. The remote device is located remotely from the computer system and comprises a second or remote PCI bus and one or more peripheral devices coupled to the second PCI bus. The remote device also includes a secondary bridge coupled to the second PCI bus. The secondary bridge includes PCI interface circuitry for interfacing to the second PCI bus. The serial bus is coupled between the primary bridge and the secondary bridge.

Abstract: A Wide Area Serial PCI system for connecting peripheral devices to a computer. The WASP system includes a host computer system connected through a serial bus to a remote device. The serial bus can range from several meters to several kilometers or more. The host computer system includes a CPU and memory, and also includes a first Peripheral Component Interconnect (PCI) bus, also referred to as the local PCI bus. A primary bridge according to the present invention is coupled to the first PCI bus. The primary bridge includes PCI interface circuitry for interfacing to the first PCI bus. The remote device is located remotely from the computer system and comprises a second or remote PCI bus and one or more peripheral devices coupled to the second PCI bus. The remote device also includes a secondary bridge coupled to the second PCI bus. The secondary bridge includes PCI interface circuitry for interfacing to the second PCI bus. The serial bus is coupled between the primary bridge and the secondary bridge.

Abstract: A Wide Area Serial PCI system for connecting peripheral devices to a computer. The WASP system includes a host computer system connected through a serial bus to a remote device. The serial bus can range from several meters to several kilometers or more. The host computer system includes a CPU and memory, and also includes a first Peripheral Component Interconnect (PCI) bus, also referred to as the local PCI bus. A primary bridge according to the present invention is coupled to the first PCI bus. The primary bridge includes PCI interface circuitry for interfacing to the first PCI bus. The remote device is located remotely from the computer system and comprises a second or remote PCI bus and one or more peripheral devices coupled to the second PCI bus. The remote device also includes a secondary bridge coupled to the second PCI bus. The secondary bridge includes PCI interface circuitry for interfacing to the second PCI bus. The serial bus is coupled between the primary bridge and the secondary bridge.

Abstract: A system and method for multiplexing the data outputs of multiple devices to a data bus using variable size multiplexers that do not require an even 2.sup.N number of inputs. This enables logical groupings of like registers to be more easily and more efficiently multiplexed together. The multiplexing system includes a plurality of registers wherein each register supplies eight bits of data to an eight-bit data bus. Register decode logic receives addresses from the bus and outputs a plurality of register select signals that select the registers during write cycles. The register select signals are also coupled with the outputs of each respective register to form an internal 9-bit bus output from each of the registers. The 9-bit bus internal output from each of the plurality of registers are coupled through one or more layers of multiplexing logic to provide an output to the eight-bit data bus. Instead of using standard 2.sup.N multiplexers with N select lines and 2.sup.

Abstract: A VXI device which intelligently monitors transactions on the VXI bus and begins early cycles on the bus where possible, thereby improving system performance. The VXI 0device includes a VXI bus master device and a VME bus requester. When the bus master desires the bus, the VXI bus master issues a Device Wants Bus signal to its VME requester directing the requester to gain control of the VXI bus for the device or master. The VME requester then attempts to gain control of the bus for the bus master. According to the present invention, the VME requester also monitors the VXI bus and generates the bus release signal to the master to inform the master whether it is about to lose the bus. The bus release signal provides an indication to the bus master whether the bus master can begin early cycles on the bus. Therefore, the present invention provides improved performance of VXI controllers and devices coupled to the VXI bus.