Abstract: A surgical instrument includes a rotatable electrical coupling assembly having a first part and a second part that electrically couple and rotate relative to each other. The second part is carried by and rotates with a tube collar coupled to a transducer. A portion of the transducer is inserted through an aperture of the second part, but does not contact the second part. The first part of the assembly may electrically couple to the second part via pogo pins, brush contacts, or ball bearings. Alternatively, the first part may comprise conductive channels formed in the casing. The second part may comprise a rotatable drum with a conductive trace. In some versions, one or more components may comprise MID components. In another version, the rotatable electrical coupling assembly comprises a rotatable PC board and brush contact. Further still, a circuit board may be provided with the transducer inside a transducer casing.

Abstract: A phase lock loop (PLL) circuit for controlling an oscillator includes a phase comparator, a loop filter, a reference converter and a feedback converter whose performance characteristics are dynamically controlled so as to provide a phase-locked output signal with both high frequency stepping resolution and low phase locking time. The phase comparator compares the relative phases of the reference and feedback signals, and outputs a phase difference signal representing such phase comparison. The loop filter, in accordance with a filter bandwidth dynamically selected by a filter control signal, filters the phase difference signal to provide a frequency control signal for a voltage controlled oscillator (VCO). The reference converter is a programmable frequency divider which, in accordance with a reference proportionality factor dynamically selected by a reference control signal, reduces the frequency of the PLL reference signal frequency used by the phase comparator.

Abstract: Generation of clock waveforms which have a frequency, phase offset, and duty cycle that is relative to a periodic reference signal. The outputs of a voltage controlled ring oscillator are directly applied to drive the inputs of a programmable AND, fixed OR array (PAL) to produce pulses of varied and phase offset and duty cycle. The phase offset has a resolution of one nanosecond. Additionally, the pulses generated can be ORed together within the PAL to produce clock waveforms that are multiples of the input frequency.

Abstract: A phase-locked loop having automatic internal phase offset calibration includes a voltage-controlled oscillator circuit for generating a recovered data signal in response to an error signal. A phase detector determines the phase difference between the recovered data signal and a reference data signal. The phase-locked loop further includes a charge pump circuit, coupled to the phase detector, for generating an error signal in response to the detected phase difference. The charge pump circuit includes first and second pump generators for respectively providing first and second sets of pump signals, with the pump generators being interconnected to facilitate generation of the error signal. The phase-locked loop is designed to alternate between operation in phase correction and phase calibration cycles. In each phase correction cycle an error signal is synthesized as described above on the basis of the most recent phase comparison.

Abstract: The present invention provides a CMOS output buffer with ECL output characteristics that allows the outputs to be terminated in any manner desired and which is not limited by the op amp settling time. The buffer establishes a bus internally for the VOH and VOL levels and then switches between the buses using transmission gates. In the disclosed embodiment of the invention, the op amp's feedback path includes a P-channel device which is either identical to or, to conserve power, a carefully scaled down equivalent of the P-channel output device.

Abstract: A system (100, 50, 300) for recovering a clock signal from a serial data signal (102) having rising (204) and falling (206) transitions. The transistions (204, 206) are detected by a transition detector (11, 12, 108, 110) which generates a transition signal (13a, 13b, 109, 111) having a first logic state when a rising (204) or falling (206) transition is detected. The system (100, 50, 300) includes a delay device (22, 120, 122) which delays the transition signal (13a, 13b, 109, 111) by a preselected time period and a gating device (24, 124, 126) responsive to the transition signal (13a, 13b, 109, 111). The gating device (24, 124, 126) is enabled by the transition signal (13a, 13b, 109, 111) when the signal is the first logic state, thereby permitting a system generated clock signal (148) to propagate to a phase comparison system (132, 134, 176, 178, G 1, G4) for comparison with the delayed transition signal (23, 128, 130).

Abstract: An emitter-coupled logic (ECL) gate configuration is provided that allows variations in the bias current for controlling propagation delay. The emitter coupled logic circuitry includes a plurality of input transistors having commonly-coupled emitters. The collector of each input transistor is connected to receive a control voltage. A current source is connected between the commonly-coupled emitters and ground. Circuitry, preferably a variable resistance, is connected between the collectors of the input transistors and a supply voltage. A bias voltage controls the charging current provided to the collectors of the ECL input transistors.

Abstract: A phase detector and charge pump combination is disclosed for use in a digital phase locked loop system. The phase detector includes a reset circuit that responds to the charge pump condition where it is simultaneously sourcing and sinking current. The pump up and down circuits are fast acting and balanced so that minimum conduction is employed for the phase lock condition.