Patents by Inventor Craig M Perlov

Craig M Perlov has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110309365
    Abstract: A fabrication process for a device such as a backplane for a flat panel display includes depositing thin film layers on a substrate, forming a 3D template overlying the thin film layers, and etching the 3D template and the thin film layers to form gate lines and transistors from the thin film layers. An insulating or passivation layer can then be deposited on the gate lines and the transistors, so that column or data lines can be formed on the insulating layer.
    Type: Application
    Filed: August 26, 2011
    Publication date: December 22, 2011
    Inventors: Ping Mei, Hao Luo, Albert Hua Jeans, Angeles Marcia Almanza-Workman, Robert A. Garcia, Warren Jackson, Carl P. Taussig, Craig M. Perlov
  • Patent number: 8021935
    Abstract: A fabrication process for a device such as a backplane for a flat panel display includes depositing thin film layers on a substrate, forming a 3D template overlying the thin film layers, and etching the 3D template and the thin film layers to form gate lines and transistors from the thin film layers. An insulating or passivation layer can then be deposited on the gate lines and the transistors, so that column or data lines can be formed on the insulating layer.
    Type: Grant
    Filed: October 1, 2008
    Date of Patent: September 20, 2011
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Ping Mei, Hao Luo, Albert Hua Jeans, Angeles Marcia Almanza-Workman, Robert A. Garcia, Warren Jackson, Carl P. Taussig, Craig M. Perlov
  • Publication number: 20100078640
    Abstract: A fabrication process for a device such as a backplane for a flat panel display includes depositing thin film layers on a substrate, forming a 3D template overlying the thin film layers, and etching the 3D template and the thin film layers to form gate lines and transistors from the thin film layers. An insulating or passivation layer can then be deposited on the gate lines and the transistors, so that column or data lines can be formed on the insulating layer.
    Type: Application
    Filed: October 1, 2008
    Publication date: April 1, 2010
    Inventors: Ping Mei, Hao Luo, Albert Hua Jeans, Angeles Marcia Almanza-Workman, Robert A. Garcia, Warren Jackson, Carl P. Taussig, Craig M. Perlov
  • Patent number: 7678626
    Abstract: A method of forming a thin film device on a flexible substrate is disclosed. The method includes depositing an imprintable material over the flexible substrate. The imprintable are stamped material forming a three-dimensional pattern in the imprintable material. A sacrificial layer is formed over the three-dimensional pattern. A conductive layer is deposited over the sacrificial layer. The sacrificial layer is removed, leaving portions of the conductive layer as defined by the three-dimensional pattern.
    Type: Grant
    Filed: November 23, 2005
    Date of Patent: March 16, 2010
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Craig M. Perlov, Ping Mei
  • Patent number: 7541227
    Abstract: Thin film devices and methods for forming the same are disclosed herein. A method for forming a thin film device includes forming a first at least semi-conductive strip located at a first height relative to a surface of a substrate, and forming a second at least semi-conductive strip adjacent to the first at least semi-conductive strip. The second strip is located at a second height relative to the substrate surface, and the second height is different than the first height. A nano-gap is formed between the first and second at least semi-conductive strips.
    Type: Grant
    Filed: October 30, 2006
    Date of Patent: June 2, 2009
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Ping Mei, Craig M. Perlov, Albert Hua Jeans, Carl Philip Taussig
  • Patent number: 7199025
    Abstract: The present invention provides for a common substrate with multiple sections, each constituting a separate layer of a memory device. Fold lines are arranged on the substrate to define separate sections and to provide a means for folding the sections on each other to form a multiple-layer memory device. In one application, a substrate has a fold line formed by alterations to the substrate material to form a fold line on the substrate. A first conductor section is formed with an array of parallel conductors or wires spaced across the section. A second section on the common substrate has an array of parallel conductors or wires spaced across the second section, the conductors being perpendicular to the conductors on the first section. The first and second sections are folded along the fold line over on top of each other, after a semiconductor layer has been deposited on one or both of the conductor layers, thereby forming a matrix of memory cells.
    Type: Grant
    Filed: March 14, 2005
    Date of Patent: April 3, 2007
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Craig M Perlov, Christopher A Schantz
  • Patent number: 7084007
    Abstract: The present invention provides for a common substrate with multiple sections, each constituting a separate layer of a memory device. Fold lines are arranged on the substrate to define separate sections and to provide a means for folding the sections on each other to form a multiple-layer memory device. In one application, a substrate has a fold line formed by alterations to the substrate material to form a fold line on the substrate. A first conductor section is formed with an array of parallel conductors or wires spaced across the section. A second section on the common substrate has an array of parallel conductors or wires spaced across the second section, the conductors being perpendicular to the conductors on the first section. The first and second sections are folded along the fold line over on top of each other, after a semiconductor layer has been deposited on one or both of the conductor layers, thereby forming a matrix of memory cells.
    Type: Grant
    Filed: October 30, 2003
    Date of Patent: August 1, 2006
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Craig M Perlov, Christopher A Schantz
  • Patent number: 6919633
    Abstract: The present invention provides for a common substrate with multiple sections, each constituting a separate layer of a memory device. Fold lines are arranged on the substrate to define separate sections and to provide a means for folding the sections on each other to form a multiple-layer memory device. In one application, a substrate has a fold line formed by alterations to the substrate material to form a fold line on the substrate. A first conductor section is formed with an array of parallel conductors or wires spaced across the section. A second section on the common substrate has an array of parallel conductors or wires spaced across the second section, the conductors being perpendicular to the conductors on the first section. The first and second sections are folded along the fold line over on top of each other, after a semiconductor layer has been deposited on one or both of the conductor layers, thereby forming a matrix of memory cells.
    Type: Grant
    Filed: March 7, 2001
    Date of Patent: July 19, 2005
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Craig M Perlov, Christopher A Schantz
  • Patent number: 6813182
    Abstract: A donor/acceptor-organic-junction sheet employed within an electronic memory array of a cross-point diode memory. The donor/acceptor-organic-junction sheet is anistropic with respect to flow of electrical current and is physically unstable above a threshold current. Thus, the volume of the donor/acceptor-organic-junction sheet between a row line and column line at a two-dimensional memory array grid point serves both as the diode component and as the fuse component of a diode-and-fuse memory element and is electrically insulated from similar volumes of the donor/acceptor-organic-junction sheet between neighboring grid point intersections.
    Type: Grant
    Filed: May 31, 2002
    Date of Patent: November 2, 2004
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Craig M Perlov, Stephen Forrest
  • Publication number: 20040090845
    Abstract: The present invention provides for a common substrate with multiple sections, each constituting a separate layer of a memory device. Fold lines are arranged on the substrate to define separate sections and to provide a means for folding the sections on each other to form a multiple-layer memory device. In one application, a substrate has a fold line formed by alterations to the substrate material to form a fold line on the substrate. A first conductor section is formed with an array of parallel conductors or wires spaced across the section. A second section on the common substrate has an array of parallel conductors or wires spaced across the second section, the conductors being perpendicular to the conductors on the first section. The first and second sections are folded along the fold line over on top of each other, after a semiconductor layer has been deposited on one or both of the conductor layers, thereby forming a matrix of memory cells.
    Type: Application
    Filed: October 30, 2003
    Publication date: May 13, 2004
    Applicant: Hewlett-Packard Company
    Inventors: Craig M. Perlov, Christopher A. Schantz
  • Patent number: 6690597
    Abstract: A memory cell comprises at least two antifuses in series with a diode. Each antifuse expresses a different resistance from the others when blown, and each requires an escalating programming voltage over the last to be programmed. The antifuse structures differ in their respective geometries and materials so that a low programming voltage will blow the more sensitive fuse first, and a higher voltages will program the lesser sensitive fuses thereafter.
    Type: Grant
    Filed: April 24, 2003
    Date of Patent: February 10, 2004
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Craig M. Perlov, Ping Mei
  • Publication number: 20030223270
    Abstract: A donor/acceptor-organic-junction sheet employed within an electronic memory array of a cross-point diode memory. The donor/acceptor-organic-junction sheet is anistropic with respect to flow of electrical current and is physically unstable above a threshold current. Thus, the volume of the donor/acceptor-organic-junction sheet between a row line and column line at a two-dimensional memory array grid point serves both as the diode component and as the fuse component of a diode-and-fuse memory element and is electrically insulated from similar volumes of the donor/acceptor-organic-junction sheet between neighboring grid point intersections.
    Type: Application
    Filed: May 31, 2002
    Publication date: December 4, 2003
    Inventors: Craig M. Perlov, Stephen Forrest
  • Publication number: 20020125504
    Abstract: The present invention provides for a common substrate with multiple sections, each constituting a separate layer of a memory device. Fold lines are arranged on the substrate to define separate sections and to provide a means for folding the sections on each other to form a multiple-layer memory device. In one application, a substrate has a fold line formed by alterations to the substrate material to form a fold line on the substrate. A first conductor section is formed with an array of parallel conductors or wires spaced across the section. A second section on the common substrate has an array of parallel conductors or wires spaced across the second section, the conductors being perpendicular to the conductors on the first section. The first and second sections are folded along the fold line over on top of each other, after a semiconductor layer has been deposited on one or both of the conductor layers, thereby forming a matrix of memory cells.
    Type: Application
    Filed: March 7, 2001
    Publication date: September 12, 2002
    Inventors: Craig M. Perlov, Christopher A. Schantz
  • Patent number: 5557596
    Abstract: A storage device including many field emitters in close proximity to a storage medium, and a micromover, all in a partial vacuum. Each field emitter can generate an electron beam current. The storage medium has many storage areas on it, with each field emitter responsible for a number of storage areas. Also, each storage area can be in a number of different states to represent the information stored in that area. In storing information to the storage device, the power density of an electron beam current is increased to change the state of the storage area bombarded by the electron beam current. In reading information from the device, the power density of the electron beam current is reduced to generate a signal current from the storage area bombarded by the electron beam current. During reading, the power density is selected to be low enough so that no writing occurs. The magnitude of the signal current depends on the states of the storage area.
    Type: Grant
    Filed: July 12, 1995
    Date of Patent: September 17, 1996
    Inventors: Gary Gibson, Theodore I. Kamins, Marvin S. Keshner, Steven L. Neberhuis, Craig M. Perlov, Chung C. Yang
  • Patent number: 4897749
    Abstract: A vertically recording write probe and read ring head. A ring pole is mounted adjacent a vertical recording probe pole. The ring pole tip is made thin such that it saturates on write and does not affect performance of the probe pole. The ring pole tip is separated from the probe tip by a small read gap. The probe pole and ring pole are connected in a back gap region so that the combination reads like a conventional read head.
    Type: Grant
    Filed: March 16, 1988
    Date of Patent: January 30, 1990
    Assignee: Magnetic Peripherals Inc.
    Inventors: Craig M. Perlov, Peter K. George, Mark Jursich
  • Patent number: 4788612
    Abstract: A read write head for magnetic recording on a magnetic media includes a core having a gap with confronting surfaces. To increase the magnetic saturation properties of the head, one of the confronting surfaces is covered with a layer of material having a higher magnetic permeability than the material making up the core. An additional surface of the core is also covered with the higher magnetic permeability material to prevent the flux lines from fringing into the atmosphere at the joint. The two layers of material form an integral layer of the second higher permeability magnetic material.
    Type: Grant
    Filed: July 22, 1987
    Date of Patent: November 29, 1988
    Assignee: Magnetic Peripherals Inc.
    Inventor: Craig M. Perlov
  • Patent number: 4748525
    Abstract: A probe head for vertical recording includes a U-shaped member partially surrounding the probe and a coil supported by the U-shaped member. When the coil is energized, flux from the probe is focused to the region between the legs of the U-shaped member to greatly increase flux gradient during a write operation.
    Type: Grant
    Filed: September 14, 1987
    Date of Patent: May 31, 1988
    Assignee: Magnetic Peripherals Inc.
    Inventor: Craig M. Perlov
  • Patent number: 4667260
    Abstract: A vertical recording head includes a W-shaped core, a substrate carrying a thin film probe supported in one slot of the core, and a shield coil wound in the slots to hold the substrate and assemblage together. A non-magnetic cap forms the surface of the head over the cap, with the arrangement being such that the probe extends through the cap so the magnetic gap is as small as possible.
    Type: Grant
    Filed: March 20, 1986
    Date of Patent: May 19, 1987
    Assignee: Magnetic Peripherals Inc.
    Inventors: Craig M. Perlov, Arthur Calderon, Jr.