Patents by Inventor Craig M Perlov
Craig M Perlov has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20110309365Abstract: A fabrication process for a device such as a backplane for a flat panel display includes depositing thin film layers on a substrate, forming a 3D template overlying the thin film layers, and etching the 3D template and the thin film layers to form gate lines and transistors from the thin film layers. An insulating or passivation layer can then be deposited on the gate lines and the transistors, so that column or data lines can be formed on the insulating layer.Type: ApplicationFiled: August 26, 2011Publication date: December 22, 2011Inventors: Ping Mei, Hao Luo, Albert Hua Jeans, Angeles Marcia Almanza-Workman, Robert A. Garcia, Warren Jackson, Carl P. Taussig, Craig M. Perlov
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Patent number: 8021935Abstract: A fabrication process for a device such as a backplane for a flat panel display includes depositing thin film layers on a substrate, forming a 3D template overlying the thin film layers, and etching the 3D template and the thin film layers to form gate lines and transistors from the thin film layers. An insulating or passivation layer can then be deposited on the gate lines and the transistors, so that column or data lines can be formed on the insulating layer.Type: GrantFiled: October 1, 2008Date of Patent: September 20, 2011Assignee: Hewlett-Packard Development Company, L.P.Inventors: Ping Mei, Hao Luo, Albert Hua Jeans, Angeles Marcia Almanza-Workman, Robert A. Garcia, Warren Jackson, Carl P. Taussig, Craig M. Perlov
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Publication number: 20100078640Abstract: A fabrication process for a device such as a backplane for a flat panel display includes depositing thin film layers on a substrate, forming a 3D template overlying the thin film layers, and etching the 3D template and the thin film layers to form gate lines and transistors from the thin film layers. An insulating or passivation layer can then be deposited on the gate lines and the transistors, so that column or data lines can be formed on the insulating layer.Type: ApplicationFiled: October 1, 2008Publication date: April 1, 2010Inventors: Ping Mei, Hao Luo, Albert Hua Jeans, Angeles Marcia Almanza-Workman, Robert A. Garcia, Warren Jackson, Carl P. Taussig, Craig M. Perlov
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Patent number: 7678626Abstract: A method of forming a thin film device on a flexible substrate is disclosed. The method includes depositing an imprintable material over the flexible substrate. The imprintable are stamped material forming a three-dimensional pattern in the imprintable material. A sacrificial layer is formed over the three-dimensional pattern. A conductive layer is deposited over the sacrificial layer. The sacrificial layer is removed, leaving portions of the conductive layer as defined by the three-dimensional pattern.Type: GrantFiled: November 23, 2005Date of Patent: March 16, 2010Assignee: Hewlett-Packard Development Company, L.P.Inventors: Craig M. Perlov, Ping Mei
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Patent number: 7541227Abstract: Thin film devices and methods for forming the same are disclosed herein. A method for forming a thin film device includes forming a first at least semi-conductive strip located at a first height relative to a surface of a substrate, and forming a second at least semi-conductive strip adjacent to the first at least semi-conductive strip. The second strip is located at a second height relative to the substrate surface, and the second height is different than the first height. A nano-gap is formed between the first and second at least semi-conductive strips.Type: GrantFiled: October 30, 2006Date of Patent: June 2, 2009Assignee: Hewlett-Packard Development Company, L.P.Inventors: Ping Mei, Craig M. Perlov, Albert Hua Jeans, Carl Philip Taussig
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Patent number: 7199025Abstract: The present invention provides for a common substrate with multiple sections, each constituting a separate layer of a memory device. Fold lines are arranged on the substrate to define separate sections and to provide a means for folding the sections on each other to form a multiple-layer memory device. In one application, a substrate has a fold line formed by alterations to the substrate material to form a fold line on the substrate. A first conductor section is formed with an array of parallel conductors or wires spaced across the section. A second section on the common substrate has an array of parallel conductors or wires spaced across the second section, the conductors being perpendicular to the conductors on the first section. The first and second sections are folded along the fold line over on top of each other, after a semiconductor layer has been deposited on one or both of the conductor layers, thereby forming a matrix of memory cells.Type: GrantFiled: March 14, 2005Date of Patent: April 3, 2007Assignee: Hewlett-Packard Development Company, L.P.Inventors: Craig M Perlov, Christopher A Schantz
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Patent number: 7084007Abstract: The present invention provides for a common substrate with multiple sections, each constituting a separate layer of a memory device. Fold lines are arranged on the substrate to define separate sections and to provide a means for folding the sections on each other to form a multiple-layer memory device. In one application, a substrate has a fold line formed by alterations to the substrate material to form a fold line on the substrate. A first conductor section is formed with an array of parallel conductors or wires spaced across the section. A second section on the common substrate has an array of parallel conductors or wires spaced across the second section, the conductors being perpendicular to the conductors on the first section. The first and second sections are folded along the fold line over on top of each other, after a semiconductor layer has been deposited on one or both of the conductor layers, thereby forming a matrix of memory cells.Type: GrantFiled: October 30, 2003Date of Patent: August 1, 2006Assignee: Hewlett-Packard Development Company, L.P.Inventors: Craig M Perlov, Christopher A Schantz
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Patent number: 6919633Abstract: The present invention provides for a common substrate with multiple sections, each constituting a separate layer of a memory device. Fold lines are arranged on the substrate to define separate sections and to provide a means for folding the sections on each other to form a multiple-layer memory device. In one application, a substrate has a fold line formed by alterations to the substrate material to form a fold line on the substrate. A first conductor section is formed with an array of parallel conductors or wires spaced across the section. A second section on the common substrate has an array of parallel conductors or wires spaced across the second section, the conductors being perpendicular to the conductors on the first section. The first and second sections are folded along the fold line over on top of each other, after a semiconductor layer has been deposited on one or both of the conductor layers, thereby forming a matrix of memory cells.Type: GrantFiled: March 7, 2001Date of Patent: July 19, 2005Assignee: Hewlett-Packard Development Company, L.P.Inventors: Craig M Perlov, Christopher A Schantz
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Diode-and-fuse memory elements for a write-once memory comprising an anisotropic semiconductor sheet
Patent number: 6813182Abstract: A donor/acceptor-organic-junction sheet employed within an electronic memory array of a cross-point diode memory. The donor/acceptor-organic-junction sheet is anistropic with respect to flow of electrical current and is physically unstable above a threshold current. Thus, the volume of the donor/acceptor-organic-junction sheet between a row line and column line at a two-dimensional memory array grid point serves both as the diode component and as the fuse component of a diode-and-fuse memory element and is electrically insulated from similar volumes of the donor/acceptor-organic-junction sheet between neighboring grid point intersections.Type: GrantFiled: May 31, 2002Date of Patent: November 2, 2004Assignee: Hewlett-Packard Development Company, L.P.Inventors: Craig M Perlov, Stephen Forrest -
Publication number: 20040090845Abstract: The present invention provides for a common substrate with multiple sections, each constituting a separate layer of a memory device. Fold lines are arranged on the substrate to define separate sections and to provide a means for folding the sections on each other to form a multiple-layer memory device. In one application, a substrate has a fold line formed by alterations to the substrate material to form a fold line on the substrate. A first conductor section is formed with an array of parallel conductors or wires spaced across the section. A second section on the common substrate has an array of parallel conductors or wires spaced across the second section, the conductors being perpendicular to the conductors on the first section. The first and second sections are folded along the fold line over on top of each other, after a semiconductor layer has been deposited on one or both of the conductor layers, thereby forming a matrix of memory cells.Type: ApplicationFiled: October 30, 2003Publication date: May 13, 2004Applicant: Hewlett-Packard CompanyInventors: Craig M. Perlov, Christopher A. Schantz
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Patent number: 6690597Abstract: A memory cell comprises at least two antifuses in series with a diode. Each antifuse expresses a different resistance from the others when blown, and each requires an escalating programming voltage over the last to be programmed. The antifuse structures differ in their respective geometries and materials so that a low programming voltage will blow the more sensitive fuse first, and a higher voltages will program the lesser sensitive fuses thereafter.Type: GrantFiled: April 24, 2003Date of Patent: February 10, 2004Assignee: Hewlett-Packard Development Company, L.P.Inventors: Craig M. Perlov, Ping Mei
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Diode-and-fuse memory elements for a write-once memory comprising an anisotropic semiconductor sheet
Publication number: 20030223270Abstract: A donor/acceptor-organic-junction sheet employed within an electronic memory array of a cross-point diode memory. The donor/acceptor-organic-junction sheet is anistropic with respect to flow of electrical current and is physically unstable above a threshold current. Thus, the volume of the donor/acceptor-organic-junction sheet between a row line and column line at a two-dimensional memory array grid point serves both as the diode component and as the fuse component of a diode-and-fuse memory element and is electrically insulated from similar volumes of the donor/acceptor-organic-junction sheet between neighboring grid point intersections.Type: ApplicationFiled: May 31, 2002Publication date: December 4, 2003Inventors: Craig M. Perlov, Stephen Forrest -
Publication number: 20020125504Abstract: The present invention provides for a common substrate with multiple sections, each constituting a separate layer of a memory device. Fold lines are arranged on the substrate to define separate sections and to provide a means for folding the sections on each other to form a multiple-layer memory device. In one application, a substrate has a fold line formed by alterations to the substrate material to form a fold line on the substrate. A first conductor section is formed with an array of parallel conductors or wires spaced across the section. A second section on the common substrate has an array of parallel conductors or wires spaced across the second section, the conductors being perpendicular to the conductors on the first section. The first and second sections are folded along the fold line over on top of each other, after a semiconductor layer has been deposited on one or both of the conductor layers, thereby forming a matrix of memory cells.Type: ApplicationFiled: March 7, 2001Publication date: September 12, 2002Inventors: Craig M. Perlov, Christopher A. Schantz
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Patent number: 5557596Abstract: A storage device including many field emitters in close proximity to a storage medium, and a micromover, all in a partial vacuum. Each field emitter can generate an electron beam current. The storage medium has many storage areas on it, with each field emitter responsible for a number of storage areas. Also, each storage area can be in a number of different states to represent the information stored in that area. In storing information to the storage device, the power density of an electron beam current is increased to change the state of the storage area bombarded by the electron beam current. In reading information from the device, the power density of the electron beam current is reduced to generate a signal current from the storage area bombarded by the electron beam current. During reading, the power density is selected to be low enough so that no writing occurs. The magnitude of the signal current depends on the states of the storage area.Type: GrantFiled: July 12, 1995Date of Patent: September 17, 1996Inventors: Gary Gibson, Theodore I. Kamins, Marvin S. Keshner, Steven L. Neberhuis, Craig M. Perlov, Chung C. Yang
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Patent number: 4897749Abstract: A vertically recording write probe and read ring head. A ring pole is mounted adjacent a vertical recording probe pole. The ring pole tip is made thin such that it saturates on write and does not affect performance of the probe pole. The ring pole tip is separated from the probe tip by a small read gap. The probe pole and ring pole are connected in a back gap region so that the combination reads like a conventional read head.Type: GrantFiled: March 16, 1988Date of Patent: January 30, 1990Assignee: Magnetic Peripherals Inc.Inventors: Craig M. Perlov, Peter K. George, Mark Jursich
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Patent number: 4788612Abstract: A read write head for magnetic recording on a magnetic media includes a core having a gap with confronting surfaces. To increase the magnetic saturation properties of the head, one of the confronting surfaces is covered with a layer of material having a higher magnetic permeability than the material making up the core. An additional surface of the core is also covered with the higher magnetic permeability material to prevent the flux lines from fringing into the atmosphere at the joint. The two layers of material form an integral layer of the second higher permeability magnetic material.Type: GrantFiled: July 22, 1987Date of Patent: November 29, 1988Assignee: Magnetic Peripherals Inc.Inventor: Craig M. Perlov
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Patent number: 4748525Abstract: A probe head for vertical recording includes a U-shaped member partially surrounding the probe and a coil supported by the U-shaped member. When the coil is energized, flux from the probe is focused to the region between the legs of the U-shaped member to greatly increase flux gradient during a write operation.Type: GrantFiled: September 14, 1987Date of Patent: May 31, 1988Assignee: Magnetic Peripherals Inc.Inventor: Craig M. Perlov
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Patent number: 4667260Abstract: A vertical recording head includes a W-shaped core, a substrate carrying a thin film probe supported in one slot of the core, and a shield coil wound in the slots to hold the substrate and assemblage together. A non-magnetic cap forms the surface of the head over the cap, with the arrangement being such that the probe extends through the cap so the magnetic gap is as small as possible.Type: GrantFiled: March 20, 1986Date of Patent: May 19, 1987Assignee: Magnetic Peripherals Inc.Inventors: Craig M. Perlov, Arthur Calderon, Jr.