Patents by Inventor Craig M Perlov

Craig M Perlov has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7199025
    Abstract: The present invention provides for a common substrate with multiple sections, each constituting a separate layer of a memory device. Fold lines are arranged on the substrate to define separate sections and to provide a means for folding the sections on each other to form a multiple-layer memory device. In one application, a substrate has a fold line formed by alterations to the substrate material to form a fold line on the substrate. A first conductor section is formed with an array of parallel conductors or wires spaced across the section. A second section on the common substrate has an array of parallel conductors or wires spaced across the second section, the conductors being perpendicular to the conductors on the first section. The first and second sections are folded along the fold line over on top of each other, after a semiconductor layer has been deposited on one or both of the conductor layers, thereby forming a matrix of memory cells.
    Type: Grant
    Filed: March 14, 2005
    Date of Patent: April 3, 2007
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Craig M Perlov, Christopher A Schantz
  • Patent number: 7084007
    Abstract: The present invention provides for a common substrate with multiple sections, each constituting a separate layer of a memory device. Fold lines are arranged on the substrate to define separate sections and to provide a means for folding the sections on each other to form a multiple-layer memory device. In one application, a substrate has a fold line formed by alterations to the substrate material to form a fold line on the substrate. A first conductor section is formed with an array of parallel conductors or wires spaced across the section. A second section on the common substrate has an array of parallel conductors or wires spaced across the second section, the conductors being perpendicular to the conductors on the first section. The first and second sections are folded along the fold line over on top of each other, after a semiconductor layer has been deposited on one or both of the conductor layers, thereby forming a matrix of memory cells.
    Type: Grant
    Filed: October 30, 2003
    Date of Patent: August 1, 2006
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Craig M Perlov, Christopher A Schantz
  • Patent number: 6919633
    Abstract: The present invention provides for a common substrate with multiple sections, each constituting a separate layer of a memory device. Fold lines are arranged on the substrate to define separate sections and to provide a means for folding the sections on each other to form a multiple-layer memory device. In one application, a substrate has a fold line formed by alterations to the substrate material to form a fold line on the substrate. A first conductor section is formed with an array of parallel conductors or wires spaced across the section. A second section on the common substrate has an array of parallel conductors or wires spaced across the second section, the conductors being perpendicular to the conductors on the first section. The first and second sections are folded along the fold line over on top of each other, after a semiconductor layer has been deposited on one or both of the conductor layers, thereby forming a matrix of memory cells.
    Type: Grant
    Filed: March 7, 2001
    Date of Patent: July 19, 2005
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Craig M Perlov, Christopher A Schantz
  • Patent number: 6813182
    Abstract: A donor/acceptor-organic-junction sheet employed within an electronic memory array of a cross-point diode memory. The donor/acceptor-organic-junction sheet is anistropic with respect to flow of electrical current and is physically unstable above a threshold current. Thus, the volume of the donor/acceptor-organic-junction sheet between a row line and column line at a two-dimensional memory array grid point serves both as the diode component and as the fuse component of a diode-and-fuse memory element and is electrically insulated from similar volumes of the donor/acceptor-organic-junction sheet between neighboring grid point intersections.
    Type: Grant
    Filed: May 31, 2002
    Date of Patent: November 2, 2004
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Craig M Perlov, Stephen Forrest