Patents by Inventor Craig M. Peterson

Craig M. Peterson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5552725
    Abstract: An improved power-on reset circuit is provided for controlling reset signal transition until after the power supply has achieved operational levels. Specifically, the reset signal is designated to transition from a high to a low state after the power supply exceeds a fixed reference voltage. The reference voltage is set at a voltage value greater than the operational voltage level of devices within a load circuit connected to the output of the power-on reset circuit. The power-on reset circuit includes numerous subcircuits used to define the reference voltage, trigger the reference voltage in relation to the power supply voltage, delay the triggered voltage, and buffer the delayed, triggered voltage to a reset value capable of driving load circuit impedances.
    Type: Grant
    Filed: August 5, 1994
    Date of Patent: September 3, 1996
    Assignee: Advanced Micro Devices, Inc.
    Inventors: S. Doug Ray, Craig M. Peterson
  • Patent number: 5329175
    Abstract: A reduced noise, low power, high speed output buffer circuit is provided for driving a load. The output buffer circuit utilizes multiple stage pull-up and pull-down transistors. During the time in which the first stage pull-down (or pull-up) transistor is activated, all of the opposing pull-up (or pull-down) transistors are deactivated at substantially the same time. Thereafter, the remaining stages of pull-down (or pull-up) transistors are activated. Delayed turn on in conjunction with rapid turn off achieves low overshoot and undershoot noise transient levels at the power supplies.
    Type: Grant
    Filed: November 13, 1992
    Date of Patent: July 12, 1994
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Craig M. Peterson
  • Patent number: 5103118
    Abstract: An anti-noise circuit dissipates parasitic tank circuit energy which causes ground unershoot and V.sub.cc overshoot in the power rails (PG,PV) of an integrated circuit device. An anti-noise circuit transistor element, either an anti-undershoot circuit transistor element (AUCT) or an anti-overshoot circuit transistor element (AOCT) incorporates selected resistance in its primary current path for providing dissipating resistance. The anti-noise circuit couples a current source (PV), the anti-noise circuit transistor element (AUCT, AOCT) with dissipating resistance, and power rail parasitic lead inductance in series in a sacrificial current path. A control circuit coupled to the control node of the anti-noise circuit transistor element (AUCT,AOCT) causes sacrificial current flow following switching of potential levels at the output for dissipating parasitic tank circuit energy. The control circuit incorporates an active pullup and pulldown passgate (RST1,ICT1,OCT1) (RST2,ICT3, OCT2) between the data input (V.
    Type: Grant
    Filed: November 19, 1990
    Date of Patent: April 7, 1992
    Assignee: National Semiconductor Corporation
    Inventor: Craig M. Peterson