Patents by Inventor Craig MacKenna

Craig MacKenna has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8392641
    Abstract: Aspects of the disclosure are directed to a system having a particularly-configured microcontroller. In one embodiment, the microcontroller includes the following: a processor; a processor data bus connected to the processor; a set of peripherals; a peripheral data bus connected to the peripherals; a peripheral bus bridge providing an interface between the processor data bus and the peripheral data base and including a plurality of special function register bank blocks that are internal to the microcontroller, each register bank block having a respective output; and a register bank block decoder circuit for decoding interrupts to provide a selection output for activation of one of the plurality of register bank blocks.
    Type: Grant
    Filed: May 24, 2010
    Date of Patent: March 5, 2013
    Assignee: NXP B.V.
    Inventors: Pankaj Shrivastava, Gregory Goodhue, Ata Khan, Zhimin Ding, Craig MacKenna
  • Patent number: 8341382
    Abstract: A microcontroller using an optimized buffer replacement strategy comprises a memory configured to store instructions, a processor configured to execute said program instructions, and a memory accelerator operatively coupled between the processor and the memory. The memory accelerator is configured to receive an information request and overwrite the buffer from which the prefetch was initiated with the requested information when the request is fulfilled by a previously initiated prefetch operation.
    Type: Grant
    Filed: September 30, 2010
    Date of Patent: December 25, 2012
    Assignee: NXP B.V.
    Inventors: Craig MacKenna, Rick Varney, Gregory Goodhue
  • Patent number: 8266369
    Abstract: Flash-type memory access and control is facilitated (e.g., as random-access memory). According to an example embodiment, an interface communicates with and controls a flash memory circuit over a peripheral interface bus. The interface uses a FIFO buffer coupled to receive data from and store data for the flash memory circuit and to provide access to the stored data. An interface controller communicates with the flash memory circuit via the peripheral interface bus to initialize the flash memory circuit and to access data thereto, in response to requests from a processor. In some applications, the flash memory circuit is initialized by sending commands to it. The interface may be placed into a read-only mode in which data in the flash memory is accessed as part of main (computer) processor memory, using the FIFO to buffer data from the flash.
    Type: Grant
    Filed: December 18, 2009
    Date of Patent: September 11, 2012
    Assignee: NXP B.V.
    Inventors: Craig MacKenna, Prithvi Nagaraj, Rob Cosaro
  • Publication number: 20120084532
    Abstract: A microcontroller using an optimized buffer replacement strategy comprises a memory configured to store instructions, a processor configured to execute said program instructions, and a memory accelerator operatively coupled between the processor and the memory. The memory accelerator is configured to receive an information request and overwrite the buffer from which the prefetch was initiated with the requested information when the request is fulfilled by a previously initiated prefetch operation.
    Type: Application
    Filed: September 30, 2010
    Publication date: April 5, 2012
    Applicant: NXP B.V.
    Inventors: Craig MaCkenna, Richard N. Varney, Gregory K. Goodhue
  • Publication number: 20110153910
    Abstract: Flash-type memory access and control is facilitated (e.g., as random-access memory). According to an example embodiment, an interface communicates with and controls a flash memory circuit over a peripheral interface bus. The interface uses a FIFO buffer coupled to receive data from and store data for the flash memory circuit and to provide access to the stored data. An interface controller communicates with the flash memory circuit via the peripheral interface bus to initialize the flash memory circuit and to access data thereto, in response to requests from a processor. In some applications, the flash memory circuit is initialized by sending commands to it. The interface may be placed into a read-only mode in which data in the flash memory is accessed as part of main (computer) processor memory, using the FIFO to buffer data from the flash.
    Type: Application
    Filed: December 18, 2009
    Publication date: June 23, 2011
    Inventors: Craig MacKenna, Prithvi Nagaraj, Rob Cosaro
  • Publication number: 20100299471
    Abstract: Aspects of the disclosure are directed to a system having a particularly-configured microcontroller. In one embodiment, the microcontroller includes the following: a processor; a processor data bus connected to the processor; a set of peripherals; a peripheral data bus connected to the peripherals; a peripheral bus bridge providing an interface between the processor data bus and the peripheral data base and including a plurality of special function register bank blocks that are internal to the microcontroller, each register bank block having a respective output; and a register bank block decoder circuit for decoding interrupts to provide a selection output for activation of one of the plurality of register bank blocks.
    Type: Application
    Filed: May 24, 2010
    Publication date: November 25, 2010
    Inventors: Pankaj Shrivastava, Gregory Goodhue, Ata khan, Zhimin Ding, Craig Mackenna
  • Publication number: 20060206646
    Abstract: Typically, for processing systems it must be guaranteed that all interrupted program stream parameters are restored before the execution of the first program stream resumes. If during this transfer an interrupt occurs, then all data may not be stored or restored. If the error free storage of the program register contents and other critical first program stream data does not occur, the processor (180) has no way of knowing whether the first program stream data restored to the registers has become corrupt or not. Thus, a novel register architecture (120, 121, 122, 123, 124, 125) is provided that facilitate processing of interrupting program streams without storing and restoring interrupted program stream critical data.
    Type: Application
    Filed: July 29, 2004
    Publication date: September 14, 2006
    Applicant: Koninklijke Philips Electronics N.V.
    Inventors: Pankaj Shrivastava, Gregory Goodhue, Ata Khan, Zhimin Ding, Craig Mackenna
  • Patent number: 6502181
    Abstract: A controller for executing instructions has one the order of five addressing modes and can allow executing of processes concurrently in multiple modes. A specific embodiment can effectively run legacy code written for the Z80 micoprocessor without requiring recompiling of code. An optional embodiment includes autonomous Multiply/Accumulator Engine (MAC) optimized to perform sum-of-products (SOP) operations with little controller overhead, making the invention capable of more effectively handling a number of processing tasks, particularly tasks related to digital signal processing (DSP).
    Type: Grant
    Filed: September 17, 1999
    Date of Patent: December 31, 2002
    Assignee: ZiLOG, Inc.
    Inventors: Craig MacKenna, Gyle Yearsley
  • Patent number: 6154793
    Abstract: An improved DMA controller is provided. The improved DMA controller uses a peripheral control bus which has scan codes to indicate the DMA channel, conventional data request/data acknowledge lines, and additional lines indicating a "terminate," "type fetch," "end of buffer" and "store status." List entries are associated with the buffers in the memory. Each list entry has a type/status field which can be coded with information indicating "ready buffer," whether to notify "end of buffer," "buffer in progress," "completed buffer without status," "completed buffer with status," "ready buffer with command," and "ready buffer without command." The type of status byte can be checked before processing the buffers.
    Type: Grant
    Filed: April 30, 1997
    Date of Patent: November 28, 2000
    Assignee: Zilog, Inc.
    Inventors: Craig MacKenna, Gyle Yearsley
  • Patent number: 5960190
    Abstract: An ICE system for emulating a device includes an EPROM storing control code, at least one RAM storing user code and data, a processor alternatively executing the control code and user code, and memory map switch logic dynamically switching the memory address map of the processor between monitor and user state configurations so as to minimally impact the target environment by maximizing the available memory address space for the user code and data when the processor is executing the user code.
    Type: Grant
    Filed: February 12, 1997
    Date of Patent: September 28, 1999
    Assignee: Zilog, Inc.
    Inventor: Craig MacKenna