Patents by Inventor Craig MCADAM

Craig MCADAM has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • CIRCUITRY FOR AND METHODS OF GAIN CONTROL
    Publication number: 20240154592
    Abstract: An integrated circuit (IC), comprising: a first input pin for receiving a first input signal; a first converter configured to convert the first input signal to a first output signal; a first gain stage configured to apply a first gain to the first output signal; gain update circuitry configured to: output a first external gain control signal to a first output pin of the IC; and subsequently output a first internal gain control signal to the first gain stage to update the first gain of the first gain stage, wherein output of the first internal gain control signal is delayed relative to output of the first external gain control signal by a first predetermined delay, the first predetermined delay to compensate for signal chain delay between the first input pin and the first gain stage, wherein the gain update circuitry comprises level detection circuitry configured to determine a signal level of the first input signal or the first output signal.
    Type: Application
    Filed: November 9, 2023
    Publication date: May 9, 2024
    Applicant: Cirrus Logic International Semiconductor Ltd.
    Inventors: Andrew J. HOWLETT, Michael CHANDLER-PAGE, David P. SINGLETON, Erich P. ZWYSSIG, Craig MCADAM
  • Chip scale package
    Patent number: 11887924
    Abstract: The present disclosure relates to a chip scale package (CSP) comprising: a first set of CSP contact balls or bumps; a second set of CSP contact balls or bumps; and a channel routing region, the channel routing region being devoid of any CSP contact balls or bumps.
    Type: Grant
    Filed: November 23, 2022
    Date of Patent: January 30, 2024
    Assignee: Cirrus Logic Inc.
    Inventors: Craig McAdam, Jonathan Taylor, Douglas Macfarlane, John Kerr, James Munger, John Pavelka, Steven A. Atherton
  • CHIP SCALE PACKAGE
    Publication number: 20230088252
    Abstract: The present disclosure relates to a chip scale package (CSP) comprising: a first set of CSP contact balls or bumps; a second set of CSP contact balls or bumps; and a channel routing region, the channel routing region being devoid of any CSP contact balls or bumps.
    Type: Application
    Filed: November 23, 2022
    Publication date: March 23, 2023
    Applicant: Cirrus Logic International Semiconductor Ltd.
    Inventors: Craig MCADAM, Jonathan TAYLOR, Douglas MACFARLANE, John KERR, James MUNGER, John PAVELKA, Steven A. ATHERTON
  • Chip scale package
    Patent number: 11562952
    Abstract: The present disclosure relates to a chip scale package (CSP) comprising: a first set of CSP contact balls or bumps; a second set of CSP contact balls or bumps; and a channel routing region, the channel routing region being devoid of any CSP contact balls or bumps.
    Type: Grant
    Filed: April 30, 2021
    Date of Patent: January 24, 2023
    Assignee: Cirrus Logic, Inc.
    Inventors: Craig McAdam, Jonathan Taylor, Douglas Macfarlane, John Kerr, James Munger, John Pavelka, Steven A. Atherton
  • CHIP SCALE PACKAGE
    Publication number: 20220246514
    Abstract: The present disclosure relates to a chip scale package (CSP) comprising: a first set of CSP contact balls or bumps; a second set of CSP contact balls or bumps; and a channel routing region, the channel routing region being devoid of any CSP contact balls or bumps.
    Type: Application
    Filed: April 30, 2021
    Publication date: August 4, 2022
    Applicant: Cirrus Logic International Semiconductor Ltd.
    Inventors: Craig MCADAM, Jonathan TAYLOR, Douglas MACFARLANE, John KERR, James MUNGER, John PAVELKA, Steven A. ATHERTON