Patents by Inventor Craig Printy

Craig Printy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220093736
    Abstract: A semiconductor device include a first semiconductor layer with a first doping concentration. A second semiconductor layer has a second doping concentration and has a first surface and a second opposing surface. The second doping concentration is higher than the first doping concentration. The first surface of the second semiconductor layer is in contact with the first semiconductor layer. A contact is on the second surface of the second semiconductor layer. The contact includes a metal and a semiconductor.
    Type: Application
    Filed: September 20, 2021
    Publication date: March 24, 2022
    Inventors: Mattias DAHLSTROM, Thomas James MOUTINHO, Craig PRINTY, Wibo VAN NOORT, Tatsuya TOMINARI
  • Publication number: 20110042778
    Abstract: One or more trenches can be formed around a first portion of a semiconductor substrate, and an insulating layer can be formed under the first portion of the semiconductor substrate. The one or more trenches and the insulating layer electrically isolate the first portion of the substrate from a second portion of the substrate. The insulating layer can be formed by forming a buried layer in the substrate, such as a silicon germanium layer in a silicon substrate. One or more first trenches through the substrate to the buried layer can be formed, and open spaces can be formed in the buried layer (such as by using an etch selective to silicon germanium over silicon). The one or more first trenches and the open spaces can optionally be filled with insulative material(s). One or more second trenches can be formed and filled to isolate the first portion of the substrate.
    Type: Application
    Filed: November 1, 2010
    Publication date: February 24, 2011
    Applicant: NATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Craig Printy, Andre P. Labonte, Jamal Ramdani
  • Patent number: 7829429
    Abstract: One or more trenches can be formed around a first portion of a semiconductor substrate, and an insulating layer can be formed under the first portion of the semiconductor substrate. The one or more trenches and the insulating layer electrically isolate the first portion of the substrate from a second portion of the substrate. The insulating layer can be formed by forming a buried layer in the substrate, such as a silicon germanium layer in a silicon substrate. One or more first trenches through the substrate to the buried layer can be formed, and open spaces can be formed in the buried layer (such as by using an etch selective to silicon germanium over silicon). The one or more first trenches and the open spaces can optionally be filled with insulative material(s). One or more second trenches can be formed and filled to isolate the first portion of the substrate.
    Type: Grant
    Filed: September 18, 2007
    Date of Patent: November 9, 2010
    Assignee: National Semiconductor Corporation
    Inventors: Craig Printy, Andre P. Labonte, Jamal Ramdani
  • Patent number: 7781295
    Abstract: A system and method is disclosed for manufacturing a bipolar junction transistor that comprises an emitter/base layer that is formed by a single deposition process. In one advantageous embodiment of the invention the emitter/base layer comprises an emitter layer that comprises an epitaxially grown mono-silicon emitter. The epitaxially grown mono-silicon emitter significantly reduces the electrical resistivity of the emitter. A non-dopant impurity such as germanium is added to the base layer to endpoint a dry plasma etch process that is applied to etch the emitter/base layer.
    Type: Grant
    Filed: July 13, 2006
    Date of Patent: August 24, 2010
    Assignee: National Semiconductor Corporation
    Inventors: Jamal Ramdani, Craig Printy, Steven J. Adler, Andre P. Labonte
  • Patent number: 7508531
    Abstract: A system and method is disclosed for measuring a germanium concentration in a semiconductor wafer for manufacturing control of BiCMOS films. Germanium is deposited over a silicon substrate layer to form a silicon germanium film. Then a rapid thermal oxidation (RTO) procedure is performed to create a layer of thermal oxide over the silicon germanium film. The thickness of the layer of thermal oxide is measured in real time using an interferometer, an ellipsometer, or a spectroscopic ellipsometer. The measured thickness of the layer of thermal oxide is correlated to a germanium concentration of the silicon germanium film using an approximately linear correlation. The correlation enables a value of the germanium concentration in the silicon germanium film to be provided in real time.
    Type: Grant
    Filed: October 4, 2007
    Date of Patent: March 24, 2009
    Assignee: National Semiconductor Corporation
    Inventors: Craig Printy, Thanas Budri
  • Patent number: 7319530
    Abstract: A system and method is disclosed for measuring a germanium concentration in a semiconductor wafer for manufacturing control of BiCMOS films. Germanium is deposited over a silicon substrate layer to form a silicon germanium film. Then a rapid thermal oxidation (RTO) procedure is performed to create a layer of thermal oxide over the silicon germanium film. The thickness of the layer of thermal oxide is measured in real time using an interferometer, an ellipsometer, or a spectroscopic ellipsometer. The measured thickness of the layer of thermal oxide is correlated to a germanium concentration of the silicon germanium film using an approximately linear correlation. The correlation enables a value of the germanium concentration in the silicon germanium film to be provided in real time.
    Type: Grant
    Filed: March 29, 2004
    Date of Patent: January 15, 2008
    Assignee: National Semiconductor Corporation
    Inventors: Craig Printy, Thanas Budri