Abstract: A system and method for improving message passing between a computer and peripheral devices is disclosed. The system and method for improving message passing between a computer and peripheral devices incorporate data checking on the command/message data and each scatter gather list element. The method in accordance with the present disclosure enables a peripheral device to check the integrity of the message and ownership of the scatter gather list element before the data is processed.

Abstract: A method for transparent debug of a hardware queue and recreation of an operational scenario comprising: use of a computer device to: monitor a plurality of inputs and outputs from a plurality of hardware queues associated as parts of a design; receive a request to save from an external source; pause one or more hardware queues upon command; receive hardware queue information from at least one of the paused hardware queues; dump said hardware queue information from at least one paused hardware queue; store the hardware queue information in a data storage connected to the computing device; compare the received information to stored data representative of a functional hardware queue; identify errors and failures in each monitored hardware queue from the comparing and; restore the hardware queue to a previous state.

Abstract: Methods and apparatus are provided for burst transfers of data between DDR memories and embedded processors during training of the PHY interface in an embedded system. An embedded system comprises an embedded processor having at least one cache controller; a memory, wherein the memory has an atomic memory access that comprises a plurality of clock edges; and a memory controller having a physical interface to convert digital signals between the embedded processor and the memory, wherein the cache controller executes a training process to determine a delay through the physical interface for each of the plurality of clock edges using a burst transfer of data. The burst transfer comprises reading a data pattern from the memory and storing the data pattern in one or more registers in the embedded processor.

Abstract: A system and method for improving message passing between a computer and peripheral devices is disclosed. The system and method for improving message passing between a computer and peripheral devices incorporate data checking on the command/message data and each scatter gather list element. The method in accordance with the present disclosure enables a peripheral device to check the integrity of the message and ownership of the scatter gather list element before the data is processed.

Abstract: A method for transparent debug of a hardware queue and recreation of an operational scenario comprising: use of a computer device to: monitor a plurality of inputs and outputs from a plurality of hardware queues associated as parts of a design; receive a request to save from an external source; pause one or more hardware queues upon command; receive hardware queue information from at least one of the paused hardware queues; dump said hardware queue information from at least one paused hardware queue; store the hardware queue information in a data storage connected to the computing device; compare the received information to stored data representative of a functional hardware queue; identify errors and failures in each monitored hardware queue from the comparing and; restore the hardware queue to a previous state.

Abstract: A method for compensating for jitter during DDR3 delay line training may include using a computer or processor to perform the steps of executing a plurality of tests for each one of a plurality of delay values for an interconnect delay between a Double-Data-Rate Three (DDR3) memory controller and a DDR3 Synchronous Dynamic Random Access Memory (SDRAM); accumulating a plurality of test results for each plurality of tests for each one of the plurality of delay values; determining a plurality of final test results, where each final test result is associated with an accumulated plurality of test results; and determining a working window edge for the interconnect delay between the DDR3 memory controller and the DDR3 SDRAM utilizing the plurality of final test results.

Abstract: Methods and apparatus are provided for burst transfers of data between DDR memories and embedded processors during training of the PHY interface in an embedded system. An embedded system comprises an embedded processor having at least one cache controller; a memory, wherein the memory has an atomic memory access that comprises a plurality of clock edges; and a memory controller having a physical interface to convert digital signals between the embedded processor and the memory, wherein the cache controller executes a training process to determine a delay through the physical interface for each of the plurality of clock edges using a burst transfer of data. The burst transfer comprises reading a data pattern from the memory and storing the data pattern in one or more registers in the embedded processor.

Abstract: A device and method are provided for testing the timing of an output signal from a circuit. The output signal can be sent from a circuit contained within a portion of an integrated circuit, and represents a response to a test pattern or stimuli applied to that circuit. The output signal is compared to an expected output signal to determine skew of that signal relative to the clocking of the circuit. Testing the output signal involves placing a characterization path within the functional path of the output signal, between the circuits being tested and an output terminal that can receive a measurement device. By placing the characterization path into the functional path, the output signal sees only a single load gate terminal of, for example, a logic gate. The reduced loading not only positively impacts the normal operation of the output signal, but also beneficially minimizes the possibility of any inaccuracies in the characterization testing.

Abstract: The present invention is a method and system for providing a scalable memory building block device. The memory building block device includes a plurality of separate memory arrays, decode logic for selecting only one bit from the plurality of memory arrays, and output means for providing only one bit as an output of the memory building block device, such that the memory building block device generates as its output only one bit.

Abstract: The present invention is a method and system for providing a scalable memory building block device. The memory building block device includes a plurality of separate memory arrays, decode logic for selecting only one bit from the plurality of memory arrays, and output means for providing only one bit as an output of the memory building block device, such that the memory building block device generates as its output only one bit.

Abstract: Disclosed is an improved hard macro design for use in an ASIC, which avoids undesirable buildup of electrostatic charge on a gate of an I/O transistor of the hard macro. The hard macro includes a port level metallic conductor of an I/O port positioned at a low level metalization layer and an electrical connection between the port level metallic conductor and a gate conductor of the I/O transistor. The electrical connection includes a first conducting section extending from the gate conductor to a top level metallic conductor at a highest level metalization layer and a second conducting section extending from the top level metallic conductor layer to the port level conductor. Antenna rule violations at the I/O port of the hard macro are eliminated due to the electrical connection between the top level metallic conductor and a diffusion region.