Abstract: A system and method integrate mask layout tools to automate the generation of mask layouts for fabricating an integrated circuit corresponding to an input netlist and a timing specification. The mask layout is generated by the method including the steps of automatically sizing transistors specified in the netlist, clustering the sized transistors into cells, generating a cell library, and placing-and-routing the cells to generate the mask layout. The system includes associated memory and stored programs, including a plurality of mask layout tools; and a processor operated by an automatic mask layout generation program for sequentially applying the plurality of mask layout tools to generate the mask layout from the input data.