Abstract: Embodiments are directed to methodologies for efficiently sampling data for analysis by a pipeline analysis algorithm. The amount of sampled data is maximized without increasing sampling overhead by sampling “non-pipeline activity” data if the subject pipeline is inactive during the sampling time. The non-pipeline activity data is selected to include overall system information that is relevant to the subject pipeline's performance but is not necessarily dependent on whether the subject pipeline is active. In some embodiments, the non-pipeline activity data allows for confirmation of a pipeline performance characteristic that must otherwise be inferred by the subsequent pipeline analysis algorithm from data sampled while the pipeline was active. In some embodiments, the non-pipeline activity data allows the pipeline analysis algorithm to analyze additional performance characteristics that cannot otherwise be inferred from the data sampled while the pipeline was active.

Abstract: Methods, systems and computer program products for measuring hardware performance are provided. Aspects include receiving an indication of a start to a hardware operation. A number of clock cycles are counted from the start of a hardware operation to the completion of the hardware operation. A first region comprising a first set of bit location is defined. A second and third region is defined each including a set of bit locations. Based on the first set of bit locations being equal to zero, a granularity flag is set to zero in the sample buffer and the second and third set of bit locations are written to the sample buffer. And based on the first set of bit locations being greater than zero, the granularity flag in the sample buffer is set to one and the first and second set of bit locations are written to the sample buffer.

Abstract: Methods, systems and computer program products for measuring hardware performance are provided. Aspects include receiving an indication of a start to a hardware operation. A number of clock cycles are counted from the start of a hardware operation to the completion of the hardware operation. A first region comprising a first set of bit location is defined. A second and third region is defined each including a set of bit locations. Based on the first set of bit locations being equal to zero, a granularity flag is set to zero in the sample buffer and the second and third set of bit locations are written to the sample buffer. And based on the first set of bit locations being greater than zero, the granularity flag in the sample buffer is set to one and the first and second set of bit locations are written to the sample buffer.

Abstract: A technique relates to enabling a multiprocessor computer system to make a non-coherent request for a cache line. A first processor core sends a non-coherent fetch to a cache. In response to a second processor core having exclusive ownership of the cache line in the cache, the first processor core receives a stale copy of the cache line in the cache based on the non-coherent fetch. The non-coherent fetch is configured to obtain the stale copy for a predefined use. Cache coherency is maintained for the cache, such that the second processor core continues to have exclusive ownership of the cache line while the first processor core receives the stale copy of the cache line.

Abstract: Scheduling memory accesses in a memory system having a multiple ranks of memory, at most r ranks of which may be powered up concurrently, in which r is less than the number of ranks. If fewer than r ranks are powered up, a subset of requested powered down ranks is powered up, such that at r ranks are powered up, the subset of requested powered down ranks to be powered up including the most frequently accessed requested powered down ranks. Then, if fewer than r ranks are powered up, a subset of unrequested powered down ranks is powered up, such that a total of at most r ranks is powered up concurrently, the subset of unrequested powered down ranks to be powered up including the most frequently accessed unrequested powered down ranks.

Abstract: A shared cache line is concurrently modified by multiple processors of a computing environment. The concurrent modification is performed based, at least, on receiving one or more architected instructions (Fetch due to Non-Coherent Store instructions) that permit multiple processors to concurrently update the shared cache line absent obtaining a lock or having exclusive ownership of the data.

Abstract: Aspects include a computer-implemented method for receiving an instruction at a processor, the instruction associated with a memory block having an address. A clear indicator that indicates whether the memory block is in a cleared state is assessed by the processor. The cleared state is a state of the memory block in which the memory block does not have any data stored therein. The method also includes determining based on the clear indicator whether the memory block is in the cleared state.

Abstract: Aspects include a computer-implemented method for receiving an instruction at a processor, the instruction associated with a memory block having an address. A clear indicator that indicates whether the memory block is in a cleared state is assessed by the processor. The cleared state is a state of the memory block in which the memory block does not have any data stored therein. The method also includes determining based on the clear indicator whether the memory block is in the cleared state.

Abstract: Scheduling memory accesses in a memory system having a multiple ranks of memory, at most r ranks of which may be powered up concurrently, in which r is less than the number of ranks. If fewer than r ranks are powered up, a subset of requested powered down ranks is powered up, such that at r ranks are powered up, the subset of requested powered down ranks to be powered up including the most frequently accessed requested powered down ranks. Then, if fewer than r ranks are powered up, a subset of unrequested powered down ranks is powered up, such that a total of at most r ranks is powered up concurrently, the subset of unrequested powered down ranks to be powered up including the most frequently accessed unrequested powered down ranks.

Abstract: Embodiments are directed to systems and methodologies for efficiently sampling data for analysis by a pipeline analysis algorithm. The amount of sampled data is maximized without increasing sampling overhead by sampling “non-pipeline activity” data if the subject pipeline is inactive during the sampling time. The non-pipeline activity data is selected to include overall system information that is relevant to the subject pipeline's performance but is not necessarily dependent on whether the subject pipeline is active. In some embodiments, the non-pipeline activity data allows for confirmation of a pipeline performance characteristic that must otherwise be inferred by the subsequent pipeline analysis algorithm from data sampled while the pipeline was active. In some embodiments, the non-pipeline activity data allows the pipeline analysis algorithm to analyze additional performance characteristics that cannot otherwise be inferred from the data sampled while the pipeline was active.

Abstract: A processor implemented method for spreading data traffic across memory controllers with respect to conditions is provided. The processor implemented method includes determining whether the memory controllers are balanced. The processor implemented method includes executing a conditional spreading with respect to the conditions when the memory controllers are determined as unbalanced. The processor implemented method includes executing an equal spreading when the memory controllers are determined as balanced.

Abstract: Methods, systems and computer program products for measuring hardware performance are provided. Aspects include receiving an indication of a start to a hardware operation. A number of clock cycles are counted from the start of a hardware operation to the completion of the hardware operation. A first region comprising a first set of bit location is defined. A second and third region is defined each including a set of bit locations. Based on the first set of bit locations being equal to zero, a granularity flag is set to zero in the sample buffer and the second and third set of bit locations are written to the sample buffer. And based on the first set of bit locations being greater than zero, the granularity flag in the sample buffer is set to one and the first and second set of bit locations are written to the sample buffer.

Abstract: Technical solutions are described for authenticating a hosting system prior to securely deploying a shrouded virtual server. An example method includes receiving, by a hypervisor, a request for a public certificate, from a client device that requested the virtual server, and sending the public certificate of the hosting system that executes the hypervisor. The method also includes receiving, in response to the public certificate being successfully authenticated by the client device using a third-party verification system, a session key based on a public key included in the public certificate. The method also includes decrypting the session key using a private key, where the private key is pre-installed in the hosting system by a manufacturer of the hosting system, and sending an acknowledgement message encrypted using the session key. The method also includes establishing a secure communication between the client device and the hypervisor using the session key.

Abstract: Scheduling memory accesses in a memory system having a multiple ranks of memory, at most r ranks of which may be powered up concurrently, in which r is less than the number of ranks. If fewer than r ranks are powered up, a subset of requested powered down ranks is powered up, such that at r ranks are powered up, the subset of requested powered down ranks to be powered up including the most frequently accessed requested powered down ranks. Then, if fewer than r ranks are powered up, a subset of unrequested powered down ranks is powered up, such that a total of at most r ranks is powered up concurrently, the subset of unrequested powered down ranks to be powered up including the most frequently accessed unrequested powered down ranks.

Abstract: Scheduling memory accesses in a memory system having a multiple ranks of memory, at most r ranks of which may be powered up concurrently, in which r is less than the number of ranks. If fewer than r ranks are powered up, a subset of requested powered down ranks is powered up, such that at r ranks are powered up, the subset of requested powered down ranks to be powered up including the most frequently accessed requested powered down ranks. Then, if fewer than r ranks are powered up, a subset of unrequested powered down ranks is powered up, such that a total of at most r ranks is powered up concurrently, the subset of unrequested powered down ranks to be powered up including the most frequently accessed unrequested powered down ranks.

Abstract: Technical solutions are described for securely deploying a shrouded virtual server. An example method includes sending, by a host manager, authentication information of a hosting system to a client device in response to a request from the client device. The \method also includes receiving a request to deploy a virtual server using a shrouded mode. The method also includes deploying a preconfigured hypervisor on the hosting system, where the preconfigured hypervisor is deployed in an immutable mode that disables changes to security settings of the preconfigured hypervisor. The method also includes deploying, by the preconfigured hypervisor, a preconfigured boot image as an instance of the virtual server on the preconfigured hypervisor. The method also includes sending, by the host manager, an identifier of the virtual server for receipt by the client device.

Abstract: Technical solutions are described for authenticating a hosting system prior to securely deploying a shrouded virtual server. An example method includes receiving, by a hypervisor, a request for a public certificate, from a client device that requested the virtual server, and sending the public certificate of the hosting system that executes the hypervisor. The method also includes receiving, in response to the public certificate being successfully authenticated by the client device using a third-party verification system, a session key based on a public key included in the public certificate. The method also includes decrypting the session key using a private key, where the private key is pre-installed in the hosting system by a manufacturer of the hosting system, and sending an acknowledgement message encrypted using the session key. The method also includes establishing a secure communication between the client device and the hypervisor using the session key.

Abstract: Technical solutions are described for authenticating a hosting system prior to securely deploying a shrouded virtual server. An example method includes receiving, by a hypervisor, a request for a public certificate, from a client device that requested the virtual server, and sending the public certificate of the hosting system that executes the hypervisor. The method also includes receiving, in response to the public certificate being successfully authenticated by the client device using a third-party verification system, a session key based on a public key included in the public certificate. The method also includes decrypting the session key using a private key, where the private key is pre-installed in the hosting system by a manufacturer of the hosting system, and sending an acknowledgement message encrypted using the session key. The method also includes establishing a secure communication between the client device and the hypervisor using the session key.

Abstract: Technical solutions are described for securely deploying a shrouded virtual server. An example method includes sending, by a host manager, authentication information of a hosting system to a client device in response to a request from the client device. The \method also includes receiving a request to deploy a virtual server using a shrouded mode. The method also includes deploying a preconfigured hypervisor on the hosting system, where the preconfigured hypervisor is deployed in an immutable mode that disables changes to security settings of the preconfigured hypervisor. The method also includes deploying, by the preconfigured hypervisor, a preconfigured boot image as an instance of the virtual server on the preconfigured hypervisor. The method also includes sending, by the host manager, an identifier of the virtual server for receipt by the client device.

Abstract: Technical solutions are described for securely deploying a shrouded virtual server. An example method includes sending, by a host manager, authentication information of a hosting system to a client device in response to a request from the client device. The \method also includes receiving a request to deploy a virtual server using a shrouded mode. The method also includes deploying a preconfigured hypervisor on the hosting system, where the preconfigured hypervisor is deployed in an immutable mode that disables changes to security settings of the preconfigured hypervisor. The method also includes deploying, by the preconfigured hypervisor, a preconfigured boot image as an instance of the virtual server on the preconfigured hypervisor. The method also includes sending, by the host manager, an identifier of the virtual server for receipt by the client device.