Abstract: A secure computer system (100) includes a host processor (105) for communicating a datum to a trusted bus (101). A bridge (125) connects the trusted bus (101) to an untrusted bus (102). The bridge (125) conveys the datum from the trusted bus (101) to the untrusted bus (102). A bus access monitor (200) is coupled to the trusted bus (101) and the untrusted bus (102). The bus access monitor (200) performs a method (1000, FIG. 10) for securely monitoring the untrusted bus (102), and asserting an alarm signal when address information associated with the datum fails to compare with predetermined address information. Additionally, the host processor (105) performs a method (300, FIG. 3) for self-testing the bus access monitor.

Abstract: A secure terminal includes a host (105) and slaves (125) which send and receive messages via a peripheral component interconnect (PCI) bus (130). The host allows slaves to receive messages from the host and send messages to the host. The host prevents slave-to-slave communication of messages. The host and each slave include interface logic (120) coupled to the PCI bus and a memory (200) for coupling a processor (110) to the interface logic (120). Each dual-port RAM (200) includes a first memory portion for receiving messages from a sender and a second memory portion for storing messages to be transmitted to a receiver.