Abstract: An apparatus includes hardware circuits, a front-end power supply, voltage regulators, and control circuitry. The front-end power supply generates electrical power for the hardware circuits. The front-end power supply includes power stages that generate portions of electrical power and are activated and deactivated independently. The voltage regulators are connected to an output of the front-end power supply and provide adjustable operating voltages to the hardware circuits.

Abstract: An apparatus includes hardware circuits, a front-end power supply, voltage regulators, and control circuitry. The front-end power supply generates electrical power for the hardware circuits. The front-end power supply includes power stages that generate portions of electrical power and are activated and deactivated independently. The voltage regulators are connected to an output of the front-end power supply and provide adjustable operating voltages to the hardware circuits.

Abstract: An apparatus includes hardware circuits, a front-end power supply, voltage regulators, and control circuitry. The front-end power supply generates electrical power for the hardware circuits. The front-end power supply includes power stages that generate portions of electrical power and are activated and deactivated independently. The voltage regulators are connected to an output of the front-end power supply and provide adjustable operating voltages to the hardware circuits.

Abstract: A method from managing power state transitions in a computing system is disclosed. A processor may initiate a change in power state from a first initial power state to a first new power state and, in response to initiating the change, send an initial notification to a system integrated circuit using a first communication channel, and deactivate the first communication based on responses to the initial notification. The processor may enter the first new power state in response to the deactivation of the first communication channel, and send a final notification to a management controller using a second communication channel. The management controller may send a message to the system integrated circuit upon receiving the final notification. The system integrated circuit may then transition from a second initial power state to a second new power state based on the message.

Abstract: A method from managing power state transitions in a computing system is disclosed. A processor may initiate a change in power state from a first initial power state to a first new power state and, in response to initiating the change, send an initial notification to a system integrated circuit using a first communication channel, and deactivate the first communication based on responses to the initial notification. The processor may enter the first new power state in response to the deactivation of the first communication channel, and send a final notification to a management controller using a second communication channel. The management controller may send a message to the system integrated circuit upon receiving the final notification. The system integrated circuit may then transition from a second initial power state to a second new power state based on the message.

Abstract: Particular embodiments described herein provide for a system, such as a computing system, that includes a processor operable to execute instructions associated with the electronic code, a thermal sensor operable to measure a temperature associated with a device, and a controller in communication with the thermal sensor. The controller is configured to receive an activity status associated with the processor, and receiving a temperature output value representative of a measured temperature associated with the device from the thermal sensor. The controller is further configured to provide a disable signal to the thermal sensor based upon the activity status indicating that the processor is in a reduced activity state and that the temperature output value is less than or equal to a predetermined temperature threshold value.

Abstract: Particular embodiments described herein provide for a system, such as a computing system, that includes a processor operable to execute instructions associated with the electronic code, a thermal sensor operable to measure a temperature associated with a device, and a controller in communication with the thermal sensor. The controller is configured to receive an activity status associated with the processor, and receiving a temperature output value representative of a measured temperature associated with the device from the thermal sensor. The controller is further configured to provide a disable signal to the thermal sensor based upon the activity status indicating that the processor is in a reduced activity state and that the temperature output value is less than or equal to a predetermined temperature threshold value.

Abstract: In an embodiment, a processor includes a plurality of cores and power management logic. The power management logic may be to, in response to a first break event during a reduced power state in the processor, set an exit timer based on a platform latency tolerance, block a first plurality of break events from interrupting the reduced power state, and in response to a expiration of the exit timer, terminate the reduced power state. Other embodiments are described and claimed.

Abstract: In an embodiment, a processor includes a plurality of cores and power management logic. The power management logic may be to, in response to a first break event during a reduced power state in the processor, set an exit timer based on a platform latency tolerance, block a first plurality of break events from interrupting the reduced power state, and in response to a expiration of the exit timer, terminate the reduced power state. Other embodiments are described and claimed.

Abstract: In an embodiment, a processor includes a plurality of cores and power management logic. The power management logic may be to, in response to a first break event during a reduced power state in the processor, set an exit timer based on a platform latency tolerance, block a first plurality of break events from interrupting the reduced power state, and in response to a expiration of the exit timer, terminate the reduced power state. Other embodiments are described and claimed.

Abstract: In an embodiment, a processor includes a plurality of cores and power management logic. The power management logic may be to, in response to a first break event during a reduced power state in the processor, set an exit timer based on a platform latency tolerance, block a first plurality of break events from interrupting the reduced power state, and in response to a expiration of the exit timer, terminate the reduced power state. Other embodiments are described and claimed.

Abstract: Particular embodiments described herein provide for a system, such as a computing system, that includes a processor operable to execute instructions associated with the electronic code, a thermal sensor operable to measure a temperature associated with a device, and a controller in communication with the thermal sensor. The controller is configured to receive an activity status associated with the processor, and receiving a temperature output value representative of a measured temperature associated with the device from the thermal sensor. The controller is further configured to provide a disable signal to the thermal sensor based upon the activity status indicating that the processor is in a reduced activity state and that the temperature output value is less than or equal to a predetermined temperature threshold value.