Patents by Inventor Craig S. Jones

Craig S. Jones has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10176137
    Abstract: A selectively transparent bridge facilitates a PCI device presenting itself to the host as a PCI-to-PCI bridge but selectively hiding and isolating hardware from the host bus. PCI configuration may be achieved through the standard PCI Express configuration mechanisms, but instead of configuring devices directly, a configuration processor in the selectively transparent bridge may intercept the configuration packets from the host, and create a virtual configuration to alter how the bus topology appears to the host. Devices are selectively hidden and managed by the configuration processor, resulting in simplified complexity and bus depth. Since the selectively transparent bridge appears to the host as a transparent bridge, no special drivers or resource preallocations are required, although the selectively transparent bridge fully supports special drivers and/or resource preallocations. Devices located/connected downstream of the bridge may therefore function with unmodified drivers.
    Type: Grant
    Filed: January 18, 2016
    Date of Patent: January 8, 2019
    Assignee: NATIONAL INSTRUMENTS CORPORATION
    Inventors: Jonathan W. Hearn, Craig S. Jones, Robert D. Ross
  • Patent number: 9703740
    Abstract: A host system may couple to a PCIe subsystem. During setup of the PCIe subsystem, the BIOS in the host system may first be informed that the devices to be coupled are not PCIe devices, and certain amount of memory is required for these devices. The BIOS may therefore not attempt to configure the devices, and may instead allocate the required memory space. When the operating system boots up, it may not attempt to configure the devices, loading a custom driver instead of an existing PCI driver to configure the bus. Once loaded, the custom driver may configure the devices, then inform the OS that there are PCIe devices in the system at the specified addresses, which may cause the OS to load and execute existing PCIe device drivers to operate/use the devices. The proprietary driver may also be used to handle traffic between the PCIe drivers and the OS.
    Type: Grant
    Filed: March 8, 2016
    Date of Patent: July 11, 2017
    Assignee: NATIONAL INSTRUMENTS CORPORATION
    Inventors: Eric R. Gardiner, Jonathan W. Hearn, Craig S. Jones, Jason D. Tongen
  • Patent number: 9652370
    Abstract: Smart bridge and use. The smart bridge includes a functional unit, memory, and a switch for routing data between a host and multiple devices using a routing table. The bridge stores a forwarding address range (FAR) as a bridge representation of hardware memory resources required by the devices. The FAR is an integer multiple of a first specified minimum size and is aligned with the first specified minimum size. The bridge representation is converted to an endpoint representation that includes multiple virtual memory resources based on a starting address of the FAR. Each virtual memory resource has a respective sub-address range with a size that is a power of 2 multiple of a second specified minimum size, which is less than the first specified minimum size, and is aligned accordingly. The endpoint representation is usable by the switch or the host to allocate the virtual memory resources to the devices.
    Type: Grant
    Filed: December 5, 2013
    Date of Patent: May 16, 2017
    Assignee: NATIONAL INSTRUMENTS CORPORATION
    Inventor: Craig S. Jones
  • Publication number: 20160188518
    Abstract: A host system may couple to a PCIe subsystem. During setup of the PCIe subsystem, the BIOS in the host system may first be informed that the devices to be coupled are not PCIe devices, and certain amount of memory is required for these devices. The BIOS may therefore not attempt to configure the devices, and may instead allocate the required memory space. When the operating system boots up, it may not attempt to configure the devices, loading a custom driver instead of an existing PCI driver to configure the bus. Once loaded, the custom driver may configure the devices, then inform the OS that there are PCIe devices in the system at the specified addresses, which may cause the OS to load and execute existing PCIe device drivers to operate/use the devices. The proprietary driver may also be used to handle traffic between the PCIe drivers and the OS.
    Type: Application
    Filed: March 8, 2016
    Publication date: June 30, 2016
    Inventors: Eric R. Gardiner, Jonathan W. Hearn, Craig S. Jones, Jason D. Tongen
  • Publication number: 20160132453
    Abstract: A selectively transparent bridge facilitates a PCI device presenting itself to the host as a PCI-to-PCI bridge but selectively hiding and isolating hardware from the host bus. PCI configuration may be achieved through the standard PCI Express configuration mechanisms, but instead of configuring devices directly, a configuration processor in the selectively transparent bridge may intercept the configuration packets from the host, and create a virtual configuration to alter how the bus topology appears to the host. Devices are selectively hidden and managed by the configuration processor, resulting in simplified complexity and bus depth. Since the selectively transparent bridge appears to the host as a transparent bridge, no special drivers or resource preallocations are required, although the selectively transparent bridge fully supports special drivers and/or resource preallocations. Devices located/connected downstream of the bridge may therefore function with unmodified drivers.
    Type: Application
    Filed: January 18, 2016
    Publication date: May 12, 2016
    Inventors: Jonathan W. Hearn, Craig S. Jones, Robert D. Ross
  • Patent number: 9311266
    Abstract: A mapping and correspondence may be established between a virtual topology and a physical topology of a PCIe subsystem, and a host may be presented with the virtual topology but not the actual physical topology. A semi transparent bridge may couple an upstream host to the PCIe subsystem that includes intermediary bridges and respective PCIe endpoints coupled downstream from the intermediary bridges. The intermediary bridges may be hidden from the host, while the respective PCIe endpoints may be visible to the host. A configuration block may provide to the upstream host, during a setup mode, first memory allocation information corresponding to the intermediary switches, responsive to the upstream host expecting second memory allocation information corresponding to the respective PCIe endpoints. The configuration block may then provide to the upstream host, during a runtime mode, the second memory allocation information, responsive to the upstream host expecting the second memory allocation information.
    Type: Grant
    Filed: June 14, 2013
    Date of Patent: April 12, 2016
    Assignee: National Instruments Corporation
    Inventors: Craig S. Jones, Jonathan W. Hearn, Jason D. Tongen
  • Patent number: 9286258
    Abstract: A host system may couple to a PCIe subsystem. During setup of the PCIe subsystem, the BIOS in the host system may first be informed that the devices to be coupled are not PCIe devices, and certain amount of memory is required for these devices. The BIOS may therefore not attempt to configure the devices, and may instead allocate the required memory space. When the operating system boots up, it may not attempt to configure the devices, loading a custom driver instead of an existing PCI driver to configure the bus. Once loaded, the custom driver may configure the devices, then inform the OS that there are PCIe devices in the system at the specified addresses, which may cause the OS to load and execute existing PCIe device drivers to operate/use the devices. The proprietary driver may also be used to handle traffic between the PCIe drivers and the OS.
    Type: Grant
    Filed: June 14, 2013
    Date of Patent: March 15, 2016
    Assignee: National Instruments Corporation
    Inventors: Eric R. Gardiner, Jonathan W. Hearn, Craig S. Jones, Jason D. Tongen
  • Patent number: 9244874
    Abstract: A selectively transparent bridge facilitates a PCI device presenting itself to the host as a PCI-to-PCI bridge but selectively hiding and isolating hardware from the host bus. PCI configuration may be achieved through the standard PCI Express configuration mechanisms, but instead of configuring devices directly, a configuration processor in the selectively transparent bridge may intercept the configuration packets from the host, and create a virtual configuration to alter how the bus topology appears to the host. Devices are selectively hidden and managed by the configuration processor, resulting in simplified complexity and bus depth. Since the selectively transparent bridge appears to the host as a transparent bridge, no special drivers or resource preallocations are required, although the selectively transparent bridge fully supports special drivers and/or resource preallocations. Devices located/connected downstream of the bridge may therefore function with unmodified drivers.
    Type: Grant
    Filed: June 14, 2013
    Date of Patent: January 26, 2016
    Assignee: National Instruments Corporation
    Inventors: Jonathan W. Hearn, Craig S. Jones, Robert D. Ross
  • Publication number: 20150161068
    Abstract: Smart bridge and use. The smart bridge includes a functional unit, memory, and a switch for routing data between a host and multiple devices using a routing table. The bridge stores a forwarding address range (FAR) as a bridge representation of hardware memory resources required by the devices. The FAR is an integer multiple of a first specified minimum size and is aligned with the first specified minimum size. The bridge representation is converted to an endpoint representation that includes multiple virtual memory resources based on a starting address of the FAR. Each virtual memory resource has a respective sub-address range with a size that is a power of 2 multiple of a second specified minimum size, which is less than the first specified minimum size, and is aligned accordingly. The endpoint representation is usable by the switch or the host to allocate the virtual memory resources to the devices.
    Type: Application
    Filed: December 5, 2013
    Publication date: June 11, 2015
    Applicant: NATIONAL INSTRUMENTS CORPORATION
    Inventor: Craig S. Jones
  • Publication number: 20140372657
    Abstract: A mapping and correspondence may be established between a virtual topology and a physical topology of a PCIe subsystem, and a host may be presented with the virtual topology but not the actual physical topology. A semi transparent bridge may couple an upstream host to the PCIe subsystem that includes intermediary bridges and respective PCIe endpoints coupled downstream from the intermediary bridges. The intermediary bridges may be hidden from the host, while the respective PCIe endpoints may be visible to the host. A configuration block may provide to the upstream host, during a setup mode, first memory allocation information corresponding to the intermediary switches, responsive to the upstream host expecting second memory allocation information corresponding to the respective PCIe endpoints. The configuration block may then provide to the upstream host, during a runtime mode, the second memory allocation information, responsive to the upstream host expecting the second memory allocation information.
    Type: Application
    Filed: June 14, 2013
    Publication date: December 18, 2014
    Inventors: Craig S. Jones, Jonathan W. Hearn, Jason D. Tongen
  • Publication number: 20140372641
    Abstract: A selectively transparent bridge facilitates a PCI device presenting itself to the host as a PCI-to-PCI bridge but selectively hiding and isolating hardware from the host bus. PCI configuration may be achieved through the standard PCI Express configuration mechanisms, but instead of configuring devices directly, a configuration processor in the selectively transparent bridge may intercept the configuration packets from the host, and create a virtual configuration to alter how the bus topology appears to the host. Devices are selectively hidden and managed by the configuration processor, resulting in simplified complexity and bus depth. Since the selectively transparent bridge appears to the host as a transparent bridge, no special drivers or resource preallocations are required, although the selectively transparent bridge fully supports special drivers and/or resource preallocations. Devices located/connected downstream of the bridge may therefore function with unmodified drivers.
    Type: Application
    Filed: June 14, 2013
    Publication date: December 18, 2014
    Inventors: Jonathan W. Hearn, Craig S. Jones, Robert D. Ross
  • Publication number: 20140372741
    Abstract: A host system may couple to a PCIe subsystem. During setup of the PCIe subsystem, the BIOS in the host system may first be informed that the devices to be coupled are not PCIe devices, and certain amount of memory is required for these devices. The BIOS may therefore not attempt to configure the devices, and may instead allocate the required memory space. When the operating system boots up, it may not attempt to configure the devices, loading a custom driver instead of an existing PCI driver to configure the bus. Once loaded, the custom driver may configure the devices, then inform the OS that there are PCIe devices in the system at the specified addresses, which may cause the OS to load and execute existing PCIe device drivers to operate/use the devices. The proprietary driver may also be used to handle traffic between the PCIe drivers and the OS.
    Type: Application
    Filed: June 14, 2013
    Publication date: December 18, 2014
    Inventors: Eric R. Gardiner, Jonathan W. Hearn, Craig S. Jones, Jason D. Tongen
  • Publication number: 20140372660
    Abstract: A PCIe subsystem may be coupled to a host by a system extender adapted to perform PCIe packet routing based on packet type. A first TLP (transport layer packet) type router may receive PCIe packets, and selectively route the PCIe packets according to the type of the packet through a corresponding path of at least two alternate paths. A second TLP type router may receive the routed packet through a first path if the PCIe packet was routed through the first path, and may receive the routed packet through a second path if the routed packet was routed through the second path. A non transparent bridge may be coupled between the first TLP type router block and the second TLP type router block along the second path, while the first path may be a pass-through path from the first TLP type router block to the second TLP type router block.
    Type: Application
    Filed: June 14, 2013
    Publication date: December 18, 2014
    Inventors: Craig S. Jones, Robert D. Ross
  • Patent number: 6116176
    Abstract: A drag-reduction system incorporated within an inwardly stepped underside of a boat hull for reducing a degree of water pressure forces exerted upon the boat hull during travel of the boat upon a body of water. A plurality of spaced apart rollers are secured at a generally aft location of the boat hull associated with the inwardly stepped underside and extend in parallel spaced apart fashion and perpendicularly to a longitudinal water flow across the boat hull experienced during propulsion of the hull. An elongate and planar shaped belt of a water impervious material having an established width and defining a continuous extending and closed loop is mounted over the plurality of spaced apart rollers. A first linearly extending location of the continuous belt is recessed within the stepped underside of the hull and a second linearly extending location is in contact with the longitudinal water flow.
    Type: Grant
    Filed: August 17, 1999
    Date of Patent: September 12, 2000
    Inventor: Craig S. Jones
  • Patent number: 6050040
    Abstract: A tile for superposition over a horizontal floor comprises a thin flat metal plate of uniform thickness with a plurality of apertures extending laterally therethrough in spaced relation to one another and to the edges of thereof and having a non-metallic insert in each of the apertures of a thickness less than the thickness of the metal portion of the tile and having an upper surface disposed below the upper surface of the metal portion of the tile.
    Type: Grant
    Filed: September 3, 1998
    Date of Patent: April 18, 2000
    Inventor: Craig S. Jones
  • Patent number: 5974544
    Abstract: A disk controller for a disk drive array which maintains two representations of all drive defects. The controller maintains a logical defect list that is used to maintain the sector remapping structure when reconstructing redundancy information. The controller also maintains a physical defect list that is used to preserve known defect information on a physical disk basis. The physical defect list stores the defects even if the logical configuration of the disks changes. When the controller of the present invention determines that a block of data is bad, the controller allocates space for the respective stripe in an alternate block, recovers the data in the stripe and writes the recovered data to the newly allocated stripe. The controller then updates the remap tables in memory with the remap information. On each disk access, the controller searches the logical defect list to determine if the access involves one or more bad blocks.
    Type: Grant
    Filed: October 1, 1996
    Date of Patent: October 26, 1999
    Assignee: Dell USA, L.P.
    Inventors: Kenneth Layton Jeffries, Craig S. Jones
  • Patent number: 5911084
    Abstract: A computer system including a host CPU, a primary PCI bus coupled to the CPU, and a bus adapter coupled to the primary PCI bus, wherein the host CPU can access peripherals comprised in the bus adapter even when the bus adapter is inoperable. The bus adapter includes a PCI to PCI interface controller which includes a primary PCI interface for coupling to the primary PCI bus and a secondary PCI interface bridge for coupling to a secondary PCI bus. Peripheral bus interface logic is coupled between the primary PCI interface and the secondary PCI interface, and this interface logic couples to various peripheral devices, including ROM/Flash memory and non-volatile static random access memory (NVSRAM). According to the present invention, a host utility executing on the CPU can access the peripheral devices without having to access the secondary PCI bus.
    Type: Grant
    Filed: February 17, 1998
    Date of Patent: June 8, 1999
    Assignee: Dell USA, L.P.
    Inventors: Craig S. Jones, Victor K. Pecone, Jay Lory
  • Patent number: 5819488
    Abstract: A relatively permanent and indestructible covering (10) utilizes a plurality of single ply tiles (12) which are bonded to a base floor surface (14) and provided with a protective coating in a single step by applying at least one protective bonding coating, such as an epoxy coating, over the top of plurality of tiles. To facilitate bonding to base floor surface, each of the plurality of tiles (12) are formed with a plurality of holes passing through the surface thereof. A color finish coating can also be provided over the top of the array of tiles by utilizing a protective bonding coating having a paint or paint-like quality. In a preferred embodiment, the tiles (12) are formed from a metal such as aluminum.
    Type: Grant
    Filed: December 29, 1995
    Date of Patent: October 13, 1998
    Inventor: Craig S. Jones
  • Patent number: 5805880
    Abstract: An essential utility routine accesses a protected computer system component by making a call to a coprocessor that performs a desired function to avoid security measures imposed by an operating system. Various suitable coprocessors include an additional coprocessor connected to a host processor running the operating system imposing the security measures such as a coprocessor on a add-in card to a computer system, a microcontroller, or a system management mode (SMM) program running on the host processor. The essential utility operates on a computer system having a processor operating under an operating system and a storage. The operating system includes software which limits access to the storage. The utility includes a coprocessor, a software interface and a utility routine. The coprocessor is connected to the storage and operative independent of the operating system for accessing the storage.
    Type: Grant
    Filed: January 26, 1996
    Date of Patent: September 8, 1998
    Assignee: Dell USA, LP
    Inventors: John J. Pearce, Craig S. Jones
  • Patent number: 5729767
    Abstract: A computer system including a host CPU, a primary PCI bus coupled to the CPU, and a bus adapter coupled to the primary PCI bus, wherein the host CPU can access peripherals comprised in the bus adapter even when the bus adapter is inoperable. The bus adapter includes a PCI to PCI interface controller which includes a primary PCI interface for coupling to the primary PCI bus and a secondary PCI interface bridge for coupling to a secondary PCI bus. Peripheral bus interface logic is coupled between the primary PCI interface and the secondary PCI interface, and this interface logic couples to various peripheral devices, including ROM/Flash memory and non-volatile static random access memory (NVSRAM). According to the present invention, a host utility executing on the CPU can access the peripheral devices without having to access the secondary PCI bus.
    Type: Grant
    Filed: October 7, 1994
    Date of Patent: March 17, 1998
    Assignee: Dell USA, L.P.
    Inventors: Craig S. Jones, Victor K. Pecone, Jay Lory