Abstract: A semiconductor device includes a memory array of static-random-access memory cells. The SRAM cells are formed using a process flow more closely associated with logic-type devices. The SRAM cells are formed using one semiconductor layer compared to at least three typically seen with SRAM cells. The SRAM cells include many features that allow its dimensions to be scaled to very small dimensions (less than 0.25 microns and possible down to 0.1 microns or even smaller). A unique process integration scheme allows formation of local interconnects (522 and 524), wherein each local interconnect (522, 524) cross couples the inverters of the SRAM and is formed within a single opening (70). Also, interconnect portions (104) of word lines are laterally offset from silicon portions (36) of the same word line, so that the interconnect portions do not interfere with bit line connections.

Abstract: A magnetic random access memory (MRAM) device is formed having a fixed magnetic layer, a free magnetic layer and a first dielectric layer between them in a recess. A metal plug and an optional second dielectric layer are also formed in the recess. The metal plug serves as a write path. A word line in the MRAM cell is the gate electrode of a transistor used to both write and read the MRAM device. To write the device a current travels in a substantially vertical direction and therefore only affects one MRAM cell, thereby not affecting adjacent cells. Data storage is thereby improved.

Abstract: A semiconductor device and its method of fabrication are disclosed. The method includes forming a first well region in a semiconductor substrate. The semiconductor substrate includes a first doped region below the first well region. The first well region and the first doped region are doped with a first type dopant and the first well region is electrically connected to the first doped region. An isolation region is formed between the first well region and the first doped region. The isolation region is electrically connected to a second well region. The isolation region and the second well region are doped with a second dopant type The second dopant type is opposite the first dopant type. In one embodiment, the first type dopant includes a p-type dopant, and the second type dopant includes an n-type dopant. The method may further include, forming a second doped region within the first well region and below the isolation region.

Abstract: A semiconductor device includes a memory array of static-random-access memory cells. The SRAM cells are formed using a process flow more closely associated with logic-type devices. The SRAM cells are formed using one semiconductor layer compared to at least three typically seen with SRAM cells. The SRAM cells include many features that allow its dimensions to be scaled to very small dimensions (less than 0.25 microns and possible down to 0.1 microns or even smaller). A unique process integration scheme allows formation of local interconnects (522 and 524), wherein each local interconnect (522, 524) cross couples the inverters of the SRAM and is formed within a single opening (70). Also, interconnect portions (104) of word lines are laterally offset from silicon portions (36) of the same word line, so that the interconnect portions do not interfere with bit line connections.

Abstract: A semiconductor device including a substrate (220) having a primary surface, a memory cell (202) provided on the substrate, the memory cell (202) including a P-channel transistor, the P-channel transistor having an N-type gate (72), and peripheral portion (204) provided on the substrate, the peripheral portion including a P-channel transistor , the P-channel transistor having a P-type gate (99). A method for forming the semiconductor device is also disclosed.

Abstract: An SRAM cell includes a pair of cross-coupled inverters where each inverter includes vertical n-channel and p-channel transistors having a gate electrode that is shared between the transistors that make up each inverter. The gate electrodes for the inverters laterally surround the channel regions of the p-channel load transistors to achieve a relatively high beta ratio without occupying a large amount of substrate surface area. Also, the gate electrodes increase the amount of capacitance of the storage nodes and decreases the soft error rate. The active regions of the latch transistors are electrically isolated from the substrate by a buried oxide layer, thereby decreasing the chances of latch-up.

Abstract: The present invention includes an integrated circuit having a self-aligned contact that makes contact to both a region within the substrate and a capacitor plate of a capacitor that is adjacent to the doped region. The present invention also includes a static-random-access memory cell with a capacitor having a first plate and a second plate. The first plate includes a first plate section of a gate electrode of a transistor, and the second plate includes a first conductive member that is substantially coincident with the first plate section. The second plate may be formed over a gate electrode of a latch transistor or over a word line. The disclosure includes methods of forming the integrated circuit and the static-random-access memory cell.

Abstract: An SRAM cell includes a pair of cross-coupled inverters where each inverter includes vertical n-channel and p-channel transistors having a gate electrode that is shared between the transistors that make up each inverter. The gate electrodes for the inverters laterally surround the channel regions of the p-channel load transistors to achieve a relatively high beta ratio without occupying a large amount of substrate surface area. Also, the gate electrodes increase the amount of capacitance of the storage nodes and decreases the soft error rate. The active regions of the latch transistors are electrically isolated from the substrate by a buried oxide layer, thereby decreasing the chances of latch-up.

Abstract: A ferromagnetic memory circuit (10) and a ferromagnetic memory device (15) which has a substrate (42). Within the substrate (42), a first current electrode (44) and a second current electrode (46) are formed. A control electrode (50) is formed to control current flow between the first and second current electrodes (44 and 46). A ferromagnetic region (68) is used to store a logic value via magnetic flux. Two conductive layers (62 and 70) and a conductive spacer (78) form a sense conductor for device (15). The sense conductor is used to externally provide the logic value stored in the device (15). A conductive layer (82) forms a program/erase line for altering the logic value stored in the device (15). A logic one or a logic zero is stored in ferromagnetic region (68) depending upon a direction and a magnitude of current flow through conductive layer (82).

Abstract: The present invention includes an integrated circuit having a self-aligned contact that makes contact to both a region within the substrate and a capacitor plate of a capacitor that is adjacent to the doped region. The present invention also includes a static-random-access memory cell with a capacitor having a first plate and a second plate. The first plate includes a first plate section of a gate electrode of a transistor, and the second plate includes a first conductive member that is substantially coincident with the first plate section. The second plate may be formed over a gate electrode of a latch transistor or over a word line. The disclosure includes methods of forming the integrated circuit and the static-random-access memory cell.

Abstract: A process for fabricating stacked gate structures (10, 11) and local interconnects (50, 52), in which portions (32, 34) of the thin-film channel layers (20, 22) are exposed by etching away portions of overlying insulating layers (28, 30). A masking layer (40) is formed to overlie the thin-film channel layers (20, 22) and the insulation layers (28, 30), and openings (42, 44) are formed in the insulation layer (40). The openings (42, 44) expose the exposed portions (32, 34) of the thin-film layers (20, 22) and portions (46, 48) of the substrate (12). Interconnects pads (50, 52) are formed to overlie the masking layer (40) and electrically contact the exposed portions of the thinfilm layers (20, 22) and the exposed portions (46,48) of the substrate (12). In regions where the insulation layers (28, 30) have not been removed, an interconnect pad (52) electrically contacts only a portion (48) of the substrate (12 ).

Abstract: A ferromagnetic memory circuit (10) and a ferromagnetic memory device (15) which has a substrate (42). Within the substrate (42), a first current electrode (44) and a second current electrode (46) are formed. A control electrode (50) is formed to control current flow between the first and second current electrodes (44 and 46). A ferromagnetic region (68) is used to store a logic value via magnetic flux. Two conductive layers (62 and 70) and a conductive spacer (78) form a sense conductor for device (15). The sense conductor is used to externally provide the logic value stored in the device (15). A conductive layer (82) forms a program/erase line for altering the logic value stored in the device (15). A logic one or a logic zero is stored in ferromagnetic region (68) depending upon a direction and a magnitude of current flow through conductive layer (82).

Abstract: In one embodiment, a semiconductor memory cell (10) having a trench (24) and access transistor (54) formed in a well region (20). The trench (24) substantially contains an inverter (60) which is electrically coupled to ground and power signals by buried layers (12, 18) in the substrate (11). The inverter (60) has a toroidal, shared-gate electrode (40) which electrically controls a driver transistor (32) in the wall (26) of the trench (24), and a thin-film load transistor (42) in the central portion of the trench (24). A portion of the toroidal, shared gate electrode extends to an adjacent well region (20') and contacts well region (20') at cell node (13'). A ground signal is provided to load transistor (42) at the bottom surface (28) of the trench (42). A supply signal is provided by a buried layer (18) which is integral with driver transistor (32).

Abstract: A method of making complementary vertical bipolar transistors and complementary field effect transistors on the same substrate is described. The process includes forming buried layers in a semiconductor substrate which are spaced apart in a self-aligned manner by use of a lateral etching technique to undercut the mask used for definition of the buried layers. In the process, the collector and base contacts of the bipolar devices and the corresponding conductivity-type sources and drains of the field effect transistors are combined to minimize processing steps. The process also includes a silicided polycrystalline silicon layer used to form resistors and contact the various transistors.