Patents by Inventor Craig S. Thrower

Craig S. Thrower has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5723992
    Abstract: An improved output driver circuit is disclosed which can be utilized when a plurality of voltage potentials are present. The output driver circuit comprises a first pull-up transistor coupled to a first voltage potential, a second pull-down transistor coupled to a second voltage potential, and a pad member coupled to the first pull-up and second pull-down transistor. The driver circuit further includes a circuit means which is coupled to the pad member and the first pull-up transistor. Accordingly, through this arrangement, the circuit substantially reduces the leakage through the first pull-up transistor when the pad member is coupled to a third voltage potential. An output driver circuit in accordance with the present invention, can be utilized in an integrated circuit environment where multiple voltages such as 3.3 volts and 5 volts are present and the output driver circuit will operate effectively because the leakage path normally associated with such circuits is substantially minimized.
    Type: Grant
    Filed: October 19, 1995
    Date of Patent: March 3, 1998
    Assignee: Aspec Technology, Inc.
    Inventors: Patrick Yin, Craig S. Thrower
  • Patent number: 5151622
    Abstract: A TTL to CMOS input buffer circuit is provided which includes a level shifting circuit including an input terminal and an output node for receiving at the input terminal an input signal at a TTL logic voltage level and for providing at the output node an output signal at a CMOS logic voltage level, the output signal being a logically inverted version of the input signal; and a first circuit for speeding a transition of the output signal from a low CMOS voltage level to a high CMOS voltage level; and a second circuit for preventing the first circuit from interfering with a transition of the output signal from the high CMOS voltage level to the low CMOS voltage level.
    Type: Grant
    Filed: November 6, 1990
    Date of Patent: September 29, 1992
    Assignee: Vitelic Corporation
    Inventors: Craig S. Thrower, King C. Wang