Abstract: An apparatus includes a collective switch hardware architecture, including an input arrangement circuit including multiple input ports and multiple outputs. The input arrangement circuit routes its multiple input ports to selected ones of its outputs. The collective switch hardware architecture includes collective reduction logic coupled to the multiple outputs of the input arrangement circuit and having multiple outputs. The collective reduction logic includes ALU(s) and arbitration and control circuitry. The ALU(s) and arbitration and control circuitry support multiple simultaneous collective operations from different collective classes, and support arbitrary input port and output port mapping to different collective classes. The collective switch hardware architecture further includes an output arrangement circuit including a multiple inputs coupled to the multiple outputs of the collective reduction logic and including multiple output ports.

Abstract: An apparatus includes a collective switch hardware architecture, including an input arrangement circuit including multiple input ports and multiple outputs. The input arrangement circuit routes its multiple input ports to selected ones of its outputs. The collective switch hardware architecture includes collective reduction logic coupled to the multiple outputs of the input arrangement circuit and having multiple outputs. The collective reduction logic includes ALU(s) and arbitration and control circuity. The ALU(s) and arbitration and control circuitry support multiple simultaneous collective operations from different collective classes, and support arbitrary input port and output port mapping to different collective classes. The collective switch hardware architecture further includes an output arrangement circuit including a multiple inputs coupled to the multiple outputs of the collective reduction logic and including multiple output ports.

Abstract: Efficient, reliable broadcast support is provided to clients of a network built using switching elements that have the capability to replicate packets. Replication patterns are generated and used in broadcasting data in the network. The replication patterns are provided in hardware of the network to enable broadcasting from one node in the network to each node of a broadcast domain of the network.

Abstract: The interconnecting network for switching data packets, having data and flow control information, comprises a local packet switch element (S1) with local input buffers (I(1,1) . . . I(1,y)) for buffering the incoming data packets, a remote packet switch element (S2) with remote input buffers (I(2,1) . . . I(2,y)) for buffering the incoming data packets, and data lines (L) for interconnecting the local and the remote packet switch elements (S1, S2). The interconnecting network further comprises a local and a remote arbiter (A1, A2) which are connected via control lines (CL) to the input buffers (I(1,1) . . . I(1,y), I(2,1) . . . I(2,y)), and which are formed such that they can provide that the flow control information is transmitted via the data lines (L) and the control lines (CL).

Abstract: A system and method are provided in which message packet header information is rapidly formatted via communications adapter hardware using script commands supplied from the internal memory of the adapter. The formatter gathers specified header information and reassembles into appropriately positioned nibbles and bytes.