Abstract: A non-volatile memory (NVM) has a silicon germanium (SiGe) drain that is progressively more heavily doped toward the surface of the substrate. The substrate is preferably silicon and the drain is formed by first forming a cavity in the substrate in the drain location. SiGe is epitaxially grown in the cavity with an increasing doping level. Thus, the PN junction between the substrate and the drain is lightly doped on both the P and N side. The drain progressively becomes more heavily doped until the maximum desired doping level is reached, and the remaining portion of the SiGe drain is doped at this maximum desired level. As a further enhancement, the perimeter of the SiGe in the substrate is the same conductivity type as that of the substrate and channel. Thus a portion of the channel is in the SiGe.

Abstract: In one embodiment, a method for discharging a semiconductor device includes providing a semiconductor substrate, forming a hole blocking dielectric layer over the semiconductor substrate, forming nanoclusters over the hole blocking dielectric layer, forming a charge trapping layer over the nanoclusters, and applying an electric field to the nanoclusters to discharge the semiconductor device. Applying the electric field may occur while applying ultraviolet (UV) light. In one embodiment, the hole blocking dielectric layer comprises forming the hole blocking dielectric layer having a thickness greater than approximately 50 Angstroms.

Abstract: Nanoclusters are blanket deposited on an integrated circuit and then removed from regions where the nanoclusters are not desired. A sacrificial layer is formed in those regions where the nanoclusters are not desired prior to the blanket deposition. The nanoclusters and the sacrificial layer are then removed. In one form, the sacrificial layer includes a deposited nitride containing or oxide containing layer. Alternatively, the sacrificial layer includes at least one of a pad oxide or a pad nitride layer previously used to form isolation regions in the substrate. Nanocluster devices and non-nanocluster devices may then be integrated onto the same integrated circuit. The use of a sacrificial layer protects underlying layers thereby preventing the degradation of performance of the subsequently formed non-nanocluster devices.

Abstract: A memory system (20) comprising a memory array (22) having a plurality of memory cells (42) arranged in rows and columns. Each memory cell (42) has a control terminal. A voltage controller (26) provides to the control terminal of a memory cell a first verify voltage signal (Vabse) during a first verify cycle or a second verify voltage signal (Vabsp) during a second verify cycle. The first verify voltage signal (Vabse) having a predetermined voltage level that corresponds substantially to a threshold voltage level of a memory cell in the array in a first state and the second verify voltage signal (Vabsp) having a predetermined voltage level that corresponds substantially to a threshold voltage level of a memory cell in the array in a second state.

Abstract: A semiconductor device (150) is formed having a first conductive member (64) overlying a field isolation region (36) that is typically less than two microns wide. Typically, the field isolation region (36) is relatively thinner compared to wider field isolation regions. The first conductive member (64) lies between the field isolation region (36) and a second conductive member (80) to shield the substrate (20). The shielding helps to increase the field threshold voltage of the field device. The invention is particularly useful in double polysilicon process flow used in forming devices operating at a potential higher than V.sub.DD. Examples of these devices include nonvolatile memories and microcontrollers having nonvolatile memory arrays.

Abstract: A non-volatile memory having a control gate (14) and a sidewall select gate (28) is illustrated. The sidewall select gate (28) is formed in conjunction with a semiconductor doped oxide (20) to form a non-volatile memory cell (7). The semiconductor element used to dope the oxide layer (20) will generally include silicon or germanium. The non-volatile memory cell (7) is programmed by storing electrons in the doped oxide (20), and is erased using band-to-band tunneling.

Abstract: A process for fabricating a graded-channel MOS device includes the formation of a masking layer (16) on the surface of a semiconductor substrate (10) and separated from the surface by a gate oxide layer (12). A first doped region (22) is formed in a channel region (20) of the semiconductor substrate (10) using the masking layer (16) as a doping mask. A second doped region (24) is formed in the channel region (20) and extends from the principal surface (14) of the semiconductor substrate (10) to the first doped region (22). A gate electrode (34) is formed within an opening (18) in the masking layer (16) and aligned to the channel region (20). Upon removal of the masking layer (16) source and drain regions (36, 38) are formed in the semiconductor substrate (10) and aligned to the gate electrode (34).