Abstract: In one embodiment, a method for discharging a semiconductor device includes providing a semiconductor substrate, forming a hole blocking dielectric layer over the semiconductor substrate, forming nanoclusters over the hole blocking dielectric layer, forming a charge trapping layer over the nanoclusters, and applying an electric field to the nanoclusters to discharge the semiconductor device. Applying the electric field may occur while applying ultraviolet (UV) light. In one embodiment, the hole blocking dielectric layer comprises forming the hole blocking dielectric layer having a thickness greater than approximately 50 Angstroms.

Abstract: A non-volatile memory (NVM) has a silicon germanium (SiGe) drain that is progressively more heavily doped toward the surface of the substrate. The substrate is preferably silicon and the drain is formed by first forming a cavity in the substrate in the drain location. SiGe is epitaxially grown in the cavity with an increasing doping level. Thus, the PN junction between the substrate and the drain is lightly doped on both the P and N side. The drain progressively becomes more heavily doped until the maximum desired doping level is reached, and the remaining portion of the SiGe drain is doped at this maximum desired level. As a further enhancement, the perimeter of the SiGe in the substrate is the same conductivity type as that of the substrate and channel. Thus a portion of the channel is in the SiGe.

Abstract: A floating gate memory cell has a floating gate in which there are two adjacent floating gate layers. The top layer is made to have a contour while leaving the lower layer substantially unchanged. An interlevel dielectric and a control gate follow the contour of the floating gate to increase capacitance between the control gate and the floating gate. The two layers of the floating gate can be polysilicon in which the top layer has the contour formed therein by use of a sacrificial layer. The sacrificial layer is formed over the bottom polysilicon layer and etched. The top polysilicon layer is formed over the sacrificial layer. Subsequent processing of the top polysilicon layer exposes the remaining portion of the sacrificial layer so it can be removed; leaving the contour in the top polysilicon layer for the interlevel dielectric and the control gate.

Abstract: Nanoclusters are blanket deposited on an integrated circuit and then removed from regions where the nanoclusters are not desired. A sacrificial layer is formed in those regions where the nanoclusters are not desired prior to the blanket deposition. The nanoclusters and the sacrificial layer are then removed. In one form, the sacrificial layer includes a deposited nitride containing or oxide containing layer. Alternatively, the sacrificial layer includes at least one of a pad oxide or a pad nitride layer previously used to form isolation regions in the substrate. Nanocluster devices and non-nanocluster devices may then be integrated onto the same integrated circuit. The use of a sacrificial layer protects underlying layers thereby preventing the degradation of performance of the subsequently formed non-nanocluster devices.

Abstract: A non volatile memory includes a plurality of transistors having a non conductive storage medium. The transistors are erased by injecting holes into the storage medium from both the source edge region and drain edge region of the transistor. In one example, the storage medium is made from silicon nitride isolated from the underlying substrate and overlying gate by silicon dioxide. The injection of holes in the storage medium generates two hole distributions having overlapping portions. The combined distribution of the overlapping portions is above at least a level of the highest concentration of program charge in the overlap region of the storage medium. In one example, the transistors are programmed by hot carrier injection. In some examples, the sources of groups of transistors of the memory are decoded.

Abstract: A semiconductor device (10) has a highly doped layer (26) having a first conductivity type uniformly implanted into the semiconductor substrate (20). An oxide-nitride-oxide structure (36, 38, 40) is formed over the semiconductor substrate (20). A halo region (46) having the first conductivity type is implanted at an angle in only a drain side of the oxide-nitride-oxide structure and extends under the oxide-nitride-oxide structure a predetermined distance from an edge of the oxide-nitride-oxide structure. A source (52) and drain (54) having a second conductivity type are implanted into the substrate (20). The resulting non-volatile memory cell provides a low natural threshold voltage to minimize threshold voltage drift during a read cycle. In addition, the use of the halo region (46) on the drain side allows a higher programming speed, and the highly doped layer (26) allows the use of a short channel device.

Abstract: A multi-bit non-volatile memory device includes a charge storage layer (14) sandwiched between two insulating layers (12 and 16) formed on a semiconductor substrate (10). A thick oxide layer (18) is formed over the charge storage layer (14) and a minimum feature sized hole is etched in the thick oxide layer (18). An opening is formed in the thick oxide layer (18). Side-wall spacers (60) formed on the inside wall of the hole over the charge storage layer have a void (62) between them that is less than the minimum feature size. The side-wall spacers (60) function to mask portions of the charge storage layer (14), when the charge storage layer is etched away, to form the two separate charge storage regions (55 and 57) under the side-wall spacers (60). The device can be manufactured using only one mask step. Separating the charge storage regions prevents lateral conduction of charge in the nitride.

Abstract: A memory has an array made up of transistors that have two charge storage regions between the channel and control gate. Each bit is made up of two charge storage regions that are from different transistors. A bit is written by first erasing all of the storage locations and then writing one of the charge storage locations that make up the bit. A pair of charge storage locations, one erased and the other programmed, is identified for each bit. The logic state of the bit is read by comparing the charge stored in the two charge storage locations that make up the bit. This comparison is achieved by generating signals representative of the charge present in the two charge storage locations. These signals are then coupled to a sense amplifier that functions as a comparator. This avoids many problems that accompany comparisons to a fixed reference.

Abstract: A memory has an array made up of transistors that have two charge storage regions between the channel and control gate. Each bit is made up of two charge storage regions that are from different transistors. A bit is written by first erasing all of the storage locations and then writing one of the charge storage locations that make up the bit. A pair of charge storage locations, one erased and the other programmed, is identified for each bit. The logic state of the bit is read by comparing the charge stored in the two charge storage locations that make up the bit. This comparison is achieved by generating signals representative of the charge present in the two charge storage locations. These signals are then coupled to a sense amplifier that functions as a comparator. This avoids many problems that accompany comparisons to a fixed reference.

Abstract: A multi-bit non-volatile memory device includes a charge storage layer (14) sandwiched between two insulating layers (12 and 16) formed on a semiconductor substrate (10). A thick oxide layer (18) is formed over the charge storage layer (14) and a minimum feature sized hole is etched in the thick oxide layer (18). An opening is formed in the thick oxide layer (18). Side-wall spacers (60) formed on the inside wall of the hole over the charge storage layer have a void (62) between them that is less than the minimum feature size. The side-wall spacers (60) function to mask portions of the charge storage layer (14), when the charge storage layer is etched away, to form the two separate charge storage regions (55 and 57) under the side-wall spacers (60). The device can be manufactured using only one mask step. Separating the charge storage regions prevents lateral conduction of charge in the nitride.

Abstract: A non-volatile memory having a thin film dielectric storage element is programmed by hot carrier injection (HCI) and erased by tunneling. The typical structure for the memory cells for this type of memory is silicon, oxide, nitride, oxide, and silicon (SONOS). The hot carrier injection provides relatively fast programming for SONOS, while the tunneling provides for erase that avoids the difficulties with the hot hole erase (HHE) type erase that generally accompanies hot carrier injection for programming. HHE is significantly more damaging to dielectrics leading to reliability issues. HHE also has a relatively narrow area of erasure that may not perfectly match the pattern for the HCI programming leaving an incomplete erasure. The tunnel erase effectively covers the entire area so there is no concern about incomplete erase. Although tunnel erase is slower than HHE, erase time is generally less critical in a system operation than is programming time.

Abstract: A technique for reducing the read gate voltage in a memory array including memory cells having a transistor for storing charge indicative of the value stored in the cell. In one example, a voltage greater than the substrate voltage is applied to the sources of the transistors of the memory cells of the array to increase the threshold voltage of a transistor due the body effect. The read gate voltage is greater than the source voltage which is greater than the substrate voltage. A non read voltage of less than the source voltage is applied to the gates of the transistors of the unselected rows to reduce leakage current. With this embodiment, the threshold voltages of transistors having an erased state can be less than 0V. With some embodiments, the read disturb caused by a gate voltage can be reduced due to the reduction in the gate voltage. In other examples, a negative voltage is applied to the gates of unselected rows to prevent leakage current.

Abstract: A technique for reducing the read gate voltage in a memory array including memory cells having a transistor for storing charge indicative of the value stored in the cell. In one example, a voltage greater than the substrate voltage is applied to the sources of the transistors of the memory cells of the array to increase the threshold voltage of a transistor due the body effect. The read gate voltage is greater than the source voltage which is greater than the substrate voltage. A non read voltage of less than the source voltage is applied to the gates of the transistors of the unselected rows to reduce leakage current. With this embodiment, the threshold voltages of transistors having an erased state can be less than 0V. With some embodiments, the read disturb caused by a gate voltage can be reduced due to the reduction in the gate voltage. In other examples, a negative voltage is applied to the gates of unselected rows to prevent leakage current.

Abstract: A non volatile memory includes a plurality of transistors having a non conductive storage medium. The transistors are erased by injecting holes into the storage medium from both the source edge region and drain edge region of the transistor. In one example, the storage medium is made from silicon nitride isolated from the underlying substrate and overlying gate by silicon dioxide. The injection of holes in the storage medium generates two hole distributions having overlapping portions. The combined distribution of the overlapping portions is above at least a level of the highest concentration of program charge in the overlap region of the storage medium. In one example, the transistors are programmed by hot carrier injection. In some examples, the sources of groups of transistors of the memory are decoded.

Abstract: A semiconductor device (10) has a highly doped layer (26) having a first conductivity type uniformly implanted into the semiconductor substrate (20). An oxide-nitride-oxide structure (36, 38, 40) is formed over the semiconductor substrate (20). A halo region (46) having the first conductivity type is implanted at an angle in only a drain side of the oxide-nitride-oxide structure and extends under the oxide-nitride-oxide structure a predetermined distance from an edge of the oxide-nitride-oxide structure. A source (52) and drain (54) having a second conductivity type are implanted into the substrate (20). The resulting non-volatile memory cell provides a low natural threshold voltage to minimize threshold voltage drift during a read cycle. In addition, the use of the halo region (46) on the drain side allows a higher programming speed, and the highly doped layer (26) allows the use of a short channel device.

Abstract: A memory device (70) that uses a non-volatile storage element (38), such as nitride, has reduced read disturb, which is the problem of tending to increase the threshold voltage of a memory device (70) during a read. To reduce this effect, the memory device (70) uses a counterdoped channel (86) to lower the natural threshold voltage of the device (70). This counterdoping can even be of sufficient dosage to reverse the conductivity type of the channel (86) and causing a negative natural threshold voltage. This allows for a lower gate voltage during read to reduce the adverse effect of performing a read. An anti-punch through (ATP) region (74) below the channel (86) allows for the lightly doped or reversed conductivity type channel (86) to avoid short channel leakage. A halo implant (46) on the drain side (54, 53) assists in hot carrier injection (HCI) so that the HCI is effective even though the channel (86) is lightly doped or of reversed conductivity type.

Abstract: A multi-bit non-volatile memory device includes a charge storage layer (14) sandwiched between two insulating layers (12 and 16) formed on a semiconductor substrate (10). A thick oxide layer (18) is formed over the charge storage layer (14) and a minimum feature sized hole is etched in the thick oxide layer (18). An opening is formed in the thick oxide layer (18). Side-wall spacers (60) formed on the inside wall of the hole over the charge storage layer have a void (62) between them that is less than the minimum feature size. The side-wall spacers (60) function to mask portions of the charge storage layer (14), when the charge storage layer is etched away, to form the two separate charge storage regions (55 and 57) under the side-wall spacers (60). The device can be manufactured using only one mask step. Separating the charge storage regions prevents lateral conduction of charge in the nitride.

Abstract: A non-volatile memory having a thin film dielectric storage element is programmed by hot carrier injection (HCI) and erased by tunneling. The typical structure for the memory cells for this type of memory is silicon, oxide, nitride, oxide, and silicon (SONOS). The hot carrier injection provides relatively fast programming for SONOS, while the tunneling provides for erase that avoids the difficulties with the hot hole erase (HHE) type erase that generally accompanies hot carrier injection for programming. HHE is significantly more damaging to dielectrics leading to reliability issues. HHE also has a relatively narrow area of erasure that may not perfectly match the pattern for the HCI programming leaving an incomplete erasure. The tunnel erase effectively covers the entire area so there is no concern about incomplete erase. Although tunnel erase is slower than HHE, erase time is generally less critical in a system operation than is programming time.

Abstract: A semiconductor device (70) includes a memory cell having a select transistor (67) and a storage transistor (65) having a relatively uniform tunnel dielectric thickness under both the floating gate (651) of the storage transistor and the select gate (671) of the select transistor (67). The select transistor (67) is adjacent to the drain region (68) for the memory cell to nearly eliminate a drain disturb problem. During programming, the control gate (652) is at a negative potential, and the drain region (68) is at a positive potential. The drain potential is sufficiently low to not degrade the tunnel dielectric layer (42) of the select transistor (67). During erase, a positive potential is applied to the control gate (652). The relatively uniform tunnel dielectric layer (42) thickness of the select transistor (67) allows for a faster operating device by increasing the read current of the memory device.

Abstract: A semiconductor device (70) includes a memory cell having a select transistor (67) and a storage transistor (65) having a relatively uniform tunnel dielectric thickness under both the floating gate (651) of the storage transistor and the select gate (671) of the select transistor (67). The select transistor (67) is adjacent to the drain region (68) for the memory cell to nearly eliminate a drain disturb problem. During programming, the control gate (652) is at a negative potential, and the drain region (68) is at a positive potential. The drain potential is sufficiently low to not degrade the tunnel dielectric layer (42) of the select transistor (67). During erase, a positive potential is applied to the control gate (652). The relatively uniform tunnel dielectric layer (42) thickness of the select transistor (67) allows for a faster operating device by increasing the read current of the memory device.