Patents by Inventor Craig Thomas Salling

Craig Thomas Salling has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7187530
    Abstract: An electrostatic discharge protective circuit may comprise a low-pass filter and a high-pass filter to receive and filter signals of a supply line. Control logic may receive output signals of the low-pass and high-pass filters and may operate a gateable channel to shunt current of the supply line dependent on the output signals from the filters.
    Type: Grant
    Filed: February 4, 2003
    Date of Patent: March 6, 2007
    Assignee: T-Ram Semiconductor, Inc.
    Inventors: Craig Thomas Salling, Siak Chon Kee, Pierre Dermy
  • Publication number: 20040125521
    Abstract: An electrostatic discharge protective circuit may comprise a low-pass filter and a high-pass filter to receive and filter signals of a supply line. Control logic may receive output signals of the low-pass and high-pass filters and may operate a gateable channel to shunt current of the supply line dependent on the output signals from the filters.
    Type: Application
    Filed: February 4, 2003
    Publication date: July 1, 2004
    Inventors: Craig Thomas Salling, Siak Chon Kee, Pierre Dermy
  • Patent number: 6449187
    Abstract: The method is for programming a memory cell in an array of cells having a plurality of bit lines, each with bit-line coupled cells, and a plurality of word lines, each with word-line coupled cells. A word line-bit line combination identifies a target cell. Each cell has a drain, source, gate and floating gate arrayed upon a base common to the cells, all of which cooperate to establish a floating gate-to-source field in each cell. The method includes the steps of: (a) applying a select signal to a word line and a bit line coupled with the target cell; (b) providing an adjusted signal to the bit-line coupled cells to decrease strength of the floating gate-to-drain field for the bit-coupled cells; (c) programming the target cell; and (d) maintaining the adjusted signal at least until the programming is complete.
    Type: Grant
    Filed: July 17, 2001
    Date of Patent: September 10, 2002
    Assignee: Texas Instruments Incorporated
    Inventors: Craig Thomas Salling, Kemal Tamer San