Abstract: A network test instrument employs at least 2 PN sequences that are applied to a network for testing. The instrument further characterizes very short cables, impedance measurement.

Abstract: An apparatus, method and data structure for validating the data bus of a microprocessor-based unit under test in which bit patterns having half as many bits as the width of the data bus are applied to the data bus along with another bit pattern which is either the complemented or true replication of the bit pattern. Evaluation of the resulting bit patterns on the data bus permits a validation of the entire width of the data bus which, if no faults are reported, obviates not only probing of the data bus by the operator but data bus diagnosis, as well. A particular data structure of a preferred bit pattern sequence avoids any fault on any data line being reported as a pass.

Abstract: A method of and system of high-speed, high-accuracy functional testing of memories in microprocessor-based units or boards under test includes a test system that is effectively permanently coupled to the unit under test bus structure during test execution and operates at the unit under test's clock rate. The test program may be stored in the unit under test's own memory, or may be electrically transferred from the test system's memory to the memory under test using a memory overlay technique.Memory testing speed may be further incresed by taking advantage of block move and compare features of newer microprocessors. An algorithm which exploits the block move and compare features is provided.