Abstract: A method of, shared register system and system for controlling access to a register are described. The shared register stores a plurality of bits including control and data bits. An access signal and a combined signal including a control portion and a data portion are received and the data portion of the combined signal is written to one or more data bits of the shared register corresponding to the control portion of the combined signal. A shared register system for controlling access to portions of a shared register includes a register having storage for bits and a register access control configured to receive an access signal and a combined signal. The register access control is operatively connected with the register to control write access to the register based on the access signal and the control portion of the combined signal.

Abstract: In one embodiment of the invention, a method for detecting a network loop problem in a network, includes: selecting a known static address of a selected device which should normally be detected at not more than one port of a downstream device; determining if the static address is detected in more than one port in a downstream device, wherein the current downstream device includes a first port which normally detects the known static address and a second port; if the static address is detected at the second port of the current downstream device, then determining the connection to the second port and if the connection to the second port is a leaf, then identifying the leaf as a misbehaving node, and if the connection to the second port is not a leaf, then evaluating a next downstream device.

Abstract: Timing of a write and read strobes for a memory having a double data rate (DDR) interface are automatically adjusted using write-read operations. A first and a second value of the write and read strobes are determined for a first write-read operation having the read data match the write data. A second write-read operation is performed for each of a plurality of third values for the write strobe at the second value for the read strobe set. A center of the third values having the read data match the write data is determined. A third write-read operation is performed for each of a plurality of fifth values for the read strobe at the fourth value of the write strobe. A center of the fifth values having the read data match the write data is determined. The timing of the write and read strobes are set to the centers.

Abstract: Timing of a write and read strobes for a memory having a double data rate (DDR) interface are automatically adjusted using write-read operations. A first and a second value of the write and read strobes are determined for a first write-read operation having the read data match the write data. A second write-read operation is performed for each of a plurality of third values for the write strobe at the second value for the read strobe set. A center of the third values having the read data match the write data is determined. A third write-read operation is performed for each of a plurality of fifth values for the read strobe at the fourth value of the write strobe. A center of the fifth values having the read data match the write data is determined. The timing of the write and read strobes are set to the centers.

Abstract: In one embodiment of the invention, a method for detecting a network loop problem in a network, includes: selecting a known static address of a selected device which should normally be detected at not more than one port of a downstream device; determining if the static address is detected in more than one port in a downstream device, wherein the current downstream device includes a first port which normally detects the known static address and a second port; if the static address is detected at the second port of the current downstream device, then determining the connection to the second port and if the connection to the second port is a leaf, then identifying the leaf as a misbehaving node, and if the connection to the second port is not a leaf, then evaluating a next downstream device.

Abstract: A method of, shared register system and system for controlling access to a register are described. The shared register stores a plurality of bits including control and data bits. An access signal and a combined signal including a control portion and a data portion are received and the data portion of the combined signal is written to one or more data bits of the shared register corresponding to the control portion of the combined signal. A shared register system for controlling access to portions of a shared register includes a register having storage for bits and a register access control configured to receive an access signal and a combined signal. The register access control is operatively connected with the register to control write access to the register based on the access signal and the control portion of the combined signal.

Abstract: One embodiment disclosed relates to a laptop computer system including a display casing, having display circuitry and a display screen, and a main computer casing coupled to the display casing. The main computer casing includes a battery power source, a charging regulator, and an Ethernet-type connector. The battery power source is coupled to a motherboard switching regulator. The charging regulator is coupled to the battery power source and configured to recharge the battery power source. The Ethernet-type connector coupled to the charging regulator and configured to provide power thereto.