Abstract: A computing device having partitions, and a method of communicating between partitions, are disclosed wherein at least one partition comprises: at least one register substantially always accessible to other partitions and capable of defining an address area; at least one address area that may be accessible to other partitions and is capable of being defined by the at least one register; and address areas other than the at least one accessible address area that are not accessible to other partitions. A method of processing interrupts comprising receiving an interrupt, assessing the origin of the interrupt, accepting, rejecting, or further assessing the interrupt, depending on its origin, when further assessing the interrupt, accepting or rejecting the interrupt depending on its contents, and forwarding accepted interrupts but not rejected interrupts to a target processor, and a device carrying out that method are also disclosed.

Abstract: Transactions are received through at least two input channels, each transaction comprising one or more data packets. The data packets are placed in a single data queue. When a first transaction received through one input channel comprises more than one data packet, a data packet of a second transaction received through another input channel is permitted to be placed in the single data queue between data packets of the first transaction. A block of space in a data output queue is assigned to each transaction. Each data packet is placed in the block assigned to its transaction.

Abstract: Delivering data from a data input to a data output within a system includes selecting a system performance parameter to be optimized, receiving at the data input a sequence of discrete data words, determining an optimum mode of delivery of the data words to the data output so as to optimize the selected performance parameter, and delivering the data words from the data input to the data output in the determined optimum mode. The optimum mode of delivery may include at least one of an optimum time and sequence of delivery of the data words.

Abstract: Distributing communications between paths, comprises providing a plurality of destinations, providing a plurality of communications paths such that each of the plurality of destinations can be accessed over each of the plurality of communications paths, defining destination addresses interleaved over the plurality of destinations, sending communications from a source to a plurality of the interleaved addresses, and selecting different ones of the plurality of paths for successive communications that are sent to addresses on different destinations, wherein the path for a communication is selected using at least a part of the address of the communication.

Abstract: Methods and apparatus in a partitionable computing system. A processor communicates with a packet former. The packet former can be configured to construct a data packet that can include security status information related to a partition or processor.

Abstract: A partitionable computer system and method of operating the same is disclosed. The partitionable computer system has a state machine, a processor, and a device controller. The state machine can be configured to monitor the status of a partition of the partitionable computer system. The information provided by the state machine can be used to provide security within the partitionable computing system.

Abstract: A method for processing an interrupt message in a system having a plurality of processors arranged into at least two partitions. The interrupt message is decoded to identify an interrupt source. If the interrupt source is not in an interrupt set, the interrupt is dropped. If the interrupt source is in a local partition, the interrupt is delivered. If the interrupt source is in the interrupt set and not in the local partition, the interrupt is processed in accordance with at least one of a target enable register and a vector enable register.

Abstract: A data communication system and method are provided to communicate in a multiprocessor interconnection network or other network. In one embodiment, the present system includes a number of logical circuits that are located in a number of nodes interconnected in a multiprocessor interconnection network. In this regard, the nodes include at least one source node, at least one destination node, and at least one intermediate node. The logical circuits include source logic located in the source nodes to identify data routes between respective source nodes and destination nodes through the one or more intermediate nodes. The data routes are specified by at least one destination port value and a current hop count that are attached to a data packet to be transmitted between respective source and destination nodes.

Abstract: A system and method for data communication in a multi-controller environment is disclosed. The system and method utilize a sequence number protocol to filter duplicate packets, adapt to transient errors, and to reroute data packets to avoid hardware malfunctions. The system and method further employ a transaction database to track packet communication in accordance with the sequence numbers. Moreover, the system and method may be implemented in hardware or software to provide a transparent transport layer to higher level hardware layers. The system and method utilize sequence number domains and a bridging protocol to reduce requirements associated with maintaining sequence number threads.

Abstract: A system and method for data communication in a multi-controller environment is disclosed. The system and method utilize a sequence number protocol to filter duplicate packets, adapt to transient errors, and to reroute data packets to avoid hardware malfunctions. The system and method further employ a transaction database to track packet communication in accordance with the sequence numbers. Moreover, the system and method may be implemented in hardware or software to provide a transparent transport layer to higher level hardware layers. The system and method utilize sequence number domains and a bridging protocol to reduce requirements associated with maintaining sequence number threads.