Abstract: In one embodiment, a processing node includes a plurality of processor cores and a reconfigurable interconnect. The processing node also includes a controller configured to schedule transactions received from each processor core. The interconnect may be coupled to convey between a first processor core and the controller, transactions that each include a first corresponding indicator that indicates the source of the transaction. The interconnect may also be coupled to convey transactions between a second processor core and the controller, transactions that each include a second corresponding indicator that indicates the source of the transaction. When operating in a first mode, the interconnect is configurable to cause the first indicator to indicate that the corresponding transactions were conveyed from the second processor core and to cause the second indicator to indicate that the corresponding transactions were conveyed from the first processor core.

Abstract: A buffer circuit which exhibits increased speed in transitions between binary states. A control transistor is coupled between a pull-up transistor and an input terminal. During low-to-high input signal transitions, the control transistor limits the signal swing at the input terminal such that small variations in the input terminal voltage result in larger voltage variations at the output terminal. During such transitions, the control transistor simultaneously decouples the input terminal from the pull-up transistor, thereby decoupling the input capacitance from the pull-up transistor. As a result, the speed with which the pull-up transistor can pull the output high is increased. As the number of input signal desired to be processed increases, the reduction in logic transition time becomes more significant. Some versions further include a pull-down transistor having a control terminal coupled to the gate of the pull-up transistor and to a power-down terminal.

Abstract: Output data points of a digital FIR filter are calculated by storing input data points in an addressable memory and accessing the addressable memory to supply a new input data point exactly once for each output data point after a first output data point and storing each input data point in a first recirculating memory for so long as that input data point is needed to calculate a next output data point. The input data points stored in the first recirculating memory are used to calculate output data points. Furthermore, coefficients are stored in a second recirculating memory and are used to calculate the output data points. As a result, only one memory access is required per output data point.

Abstract: A sequentially accessible, non-volatile data storage circuit for generating constants includes a logic array for non-volatile storage of programmed data words and a recirculating shift register for causing the first one of the data words to appear at a data output of the data storage circuit in response to a reset signal and to cause the next data word to appear at the data output in response to a clock signal.

Abstract: According to a technique for determining delays through multi-stage datapath elements, estimates of the delays through each stage of the datapath element are computed in accordance with an the equation such as:D.sub.s =D.sub.b N.sub.b +Cwhere D.sub.s is the estimated stage delay, D.sub.b is a delay associated with communication between bits in the stage, N.sub.b is the number of bits in the datapath element, and C is a constant. The estimated stage delays are used to determine positions of pipelining stages in the datapath element.