Abstract: An integrated circuit frequency generator is disclosed. In some embodiments, the frequency generator comprises an electronic oscillator configured to generate an oscillator frequency and calibration circuitry configured to periodically calibrate the electronic oscillator with respect to a reference frequency source. When a primary power source is unavailable, an output frequency is generated from the oscillator frequency, and the reference frequency source is powered-on only during calibration cycles.

Abstract: An integrated circuit frequency generator is disclosed. In some embodiments, the frequency generator comprises an electronic oscillator configured to generate an oscillator frequency and calibration circuitry configured to periodically calibrate the electronic oscillator with respect to a reference frequency source. When a primary power source is unavailable, an output frequency is generated from the oscillator frequency, and the reference frequency source is powered-on only during calibration cycles.

Abstract: An integrated circuit frequency generator is disclosed. In some embodiments, the frequency generator comprises an electronic oscillator configured to generate an oscillator frequency and calibration circuitry configured to periodically calibrate the electronic oscillator with respect to a reference frequency source. When a primary power source is unavailable, an output frequency is generated from the oscillator frequency, and the reference frequency source is powered-on only during calibration cycles.

Abstract: An integrated circuit frequency generator is disclosed. In some embodiments, the frequency generator comprises an electronic oscillator configured to generate an oscillator frequency and calibration circuitry configured to periodically calibrate the electronic oscillator with respect to a reference frequency source. When a primary power source is unavailable, an output frequency is generated from the oscillator frequency, and the reference frequency source is powered-on only during calibration cycles.

Abstract: An integrated circuit frequency generator is disclosed. In some embodiments, the frequency generator comprises an electronic oscillator configured to generate an oscillator frequency and calibration circuitry configured to periodically calibrate the electronic oscillator with respect to a reference frequency source. When a primary power source is unavailable, an output frequency is generated from the oscillator frequency, and the reference frequency source is periodically pulse powered-on to calibrate the electronic oscillator.

Abstract: A sensor system for generating sample analog signals for processing by a signal processing circuit that utilizes non-constant weights includes a plurality of signal generating elements and a switching network having a plurality of switches operably coupled to the plurality of signal generating elements. The switching network is configured to switch the plurality of signal generating elements between a plurality of different configurations. The system includes a dynamic element matching (DEM) control system for controlling the switch network to implement a second order DEM rotation scheme in which the plurality of signal generating elements are switched to each configuration in the plurality of configurations in a first sequence and then switched to each configuration in the plurality in a second sequence, the second sequence being the reverse of the first sequence.

Abstract: There are many inventions described and illustrated herein.

Abstract: There are many inventions described and illustrated herein.

Abstract: There are many inventions described and illustrated herein.

Abstract: There are many inventions described and illustrated herein.

Abstract: There are many inventions described and illustrated herein.

Abstract: There are many inventions described and illustrated herein.

Abstract: Embodiments of an oscillator circuit are described. Embodiments described herein include an oscillator circuit suitable for a resonator with relatively high motional impedance, thus requiring relatively high amplification and having relatively high sensitivity to noise. However, the embodiments described are not intended to be limited to use with any particular type of resonator. In one embodiment, alternating current (AC) coupling, or capacitive coupling, is used in part to decouple the bias voltage placed on the resonator from the operating point of the amplified, allowing one voltage to be high relative to the other. In an embodiment, some legs, or all legs of the circuit that included drive circuitry and a resonator include differential signaling.

Abstract: An amplifier drives a Digital-Subscriber Line (DSL) using a 12-volt power supply. Ordinary low-voltage transistors for 5-volt systems are stacked together to reduce the average voltage across each transistor to below a breakdown voltage. The output stage uses p-channel and n-channel driver transistors that are coupled to differential outputs through cascode transistors. A common-mode voltage is fed back to a second stage to adjust signals for deviations in the common-mode output bias. A first stage buffers a pair of differential inputs to the second stage. The second stage uses level shifting to generate four signals to the output stage driver transistors. A pair of high-voltage signals drives the p-channel drivers while a pair of low-voltage signals drives the n-channel driver transistors. Nested miller compensation stabilizes the amplifier using capacitors between the final outputs and the four signals from the second stage and the differential signals from the first stage.

Abstract: An amplifier drives a Digital-Subscriber Line (DSL) using a 12-volt power supply. Ordinary low-voltage transistors for 5-volt systems are stacked together to reduce the average voltage across each transistor to below a breakdown voltage. The output stage uses p-channel and n-channel driver transistors that are coupled to differential outputs through cascode transistors. A common-mode voltage is fed back to a second stage to adjust signals for deviations in the common-mode output bias. A first stage buffers a pair of differential inputs to the second stage. The second stage uses level shifting to generate four signals to the output stage driver transistors. A pair of high-voltage signals drives the p-channel drivers while a pair of low-voltage signals drives the n-channel driver transistors. Nested miller compensation stabilizes the amplifier using capacitors between the final outputs and the four signals from the second stage and the differential signals from the first stage.

Abstract: A digital-to-analog converter (DAC) uses switched capacitors summed, to an op amp to generate the analog output voltage. Least-significant-bits (LSBs) of the digital input switch a reference voltage to binary-weighted capacitors. The most-significant-bits (MSBs) are thermometer-coded and switch the reference voltage to capacitors that have a same size, double the size of the maximum LSB's capacitor. The thermometer-coded MSB's are scrambled before switching the same-size capacitors so that the assignment of a digital input bit to a capacitor varies from sample to sample. Any variation in capacitances for the same-size capacitors is thus spread to different digital values so that errors do not occur consistently for the same digital values. The scrambler uses radix-2 butterflies to swap bit assignments and thus outputs an even number of signals to the capacitors. Since the thermometer code is an odd number of signals, an extra signal is present that is always driven high or low.

Abstract: A segmented dual delay-locked-loop (DLL) has a coarse DLL and a fine DLL. Each DLL has a series of buffers, a phase detector, charge pump, and bias-voltage generator. The bias voltage controls the delay through the buffers. The bias voltage of the coarse DLL is adjusted by the phase comparator to lock the total delay through the buffers to be equal the input-clock period. The coarse DLL divides an input clock into M equal intervals of the input-clock period and generates M intermediate clocks having M different phases. An intermediate mux selects one of the M intermediate clocks in response to a phase-selecting address. The selected intermediate clock K and a next-following intermediate clock K+1 are both selected and applied to the fine DLL. The K clock is input to a series of N buffers in the fine DLL while the K+1 clock is directly input to a phase detector. The phase detector compares the K+1 clock to the K clock after the delay through the buffers.