Abstract: An integrated circuit (IC) includes circuitry in a plurality of power domains for transmitting and/or receiving radar chirp frames and first and second monitoring systems for monitoring supply voltages of a first and a second subset of the plurality of power domains, respectively. The first subset is monitored outside of a time window during which a chirp frame is transmitted and/or received utilizing circuitry of the IC, and the second subset is monitored during the time window. The first monitoring system includes an output for an error signal indicating a supply voltage in the first subset does not comply with a first voltage parameter. The second monitoring system includes a unique monitoring circuit for each power domain in the second subset, and each unique monitoring circuit includes an output for an error signal indicating a supply voltage in the second subset does not comply with a second voltage parameter.

Abstract: A system and method for a radar system are provided. The radar system includes a leader radar device that includes a first clock generation circuit configured to generate a first clock signal, and a first transmitter and receiver configured to transmit and receive radar signals using a first local oscillator signal. The system includes a follower radar device. The follower radar device is configured to receive the first clock signal and the first local oscillator signal from the leader radar device. The follower radar device includes a second clock generation circuit configured to generate a second clock signal, wherein, in a default operational mode of the radar system at least a portion of the second clock generation circuit is disabled, and a second transmitter and receiver configured to transmit and receive first radar signals.

Abstract: The disclosure relates to apparatus and methods for self-testing of a duty cycle detector. Example embodiments include a circuit (201) comprising: a clock signal generator (205) configured to provide an output clock signal (203) having a duty cycle; a duty cycle detector (208) arranged to receive the output clock signal (203) and provide an output flag if the duty cycle of the clock signal (203) is outside a predetermined range; a controller (214) arranged to provide a duty cycle select signal (216) to the clock signal generator (205) to cause the clock signal (203) to have a duty cycle outside the predetermined range and to receive the output flag to confirm operation of the duty cycle detector (208).

Abstract: Systems and methods are provided for performing both wireless communications and wireless sensing in combination. The systems include at least a first base station having at least one antenna device where the antenna device includes a beamformer control unit that uses a modifiable lookup table to control beam characteristics. The system may send a first set of electromagnetic sensing beams to a first environmental area within a field of view of the at least one antenna device to detect environmental objects within the environmental area. Based on data received by the antenna device, the system may generate a modified lookup table.

Abstract: The disclosure relates to a radar transceiver having a transmitter comprising a phase shifter.

Abstract: In an embodiment, there is provided a battery management method for a vehicle comprising a plurality of batteries. According to another embodiment there is a control unit for performing the battery management method. The battery management method comprising detecting an incoming hazard; predicting an impact of the incoming hazard from one or more sensors coupled to the vehicle; determining a course of action to be taken in response to the predicted impact; and controlling one or more batteries of the plurality of batteries according to the determined course of action.

Abstract: An electronic device includes a bias generator to generate a plurality of bias currents and a testing module to test the bias generator by successively testing each subset of bias currents of a plurality of subsets of bias currents grouped from the plurality of bias currents as a corresponding single test current. The testing module can include a variable resistor, wherein the testing module is to test the bias generator by, for each subset of bias currents, configuring the variable resistor to have a corresponding resistance based on the number of bias currents represented in the subset, conducting a corresponding test current through the variable resistor configured to the corresponding resistance, the test current representing a combination of all bias currents of the corresponding subset, and determining a test status for the subset of bias currents based on a voltage across the variable resistor resulting from the corresponding test current.

Abstract: Systems and methods for performing both wireless communications and wireless sensing in combination are disclosed herein. In one example embodiment, the system includes a base station (BS) including each of at least one antenna device including a first antenna device and at least one control unit. The control unit includes an input port coupled at least indirectly to the first antenna device, an output port, and a controllable circuit including each of a spillover cancellation circuit and a bypass circuit. The BS is configured to operate in each of a communication mode and a sensing mode. When the BS operates in the sensing mode, the spillover cancellation circuit of the controllable circuit is enabled and performs spillover cancellation. When the BS operates in a communication mode, the bypass circuit operates so that the spillover cancellation circuit is bypassed or otherwise does not affect how the output signal is generated.

Abstract: Systems and methods for performing both wireless communications and wireless sensing in combination are disclosed herein. In one example embodiment, the method includes sending, from a first antenna device of a base station (BS), a plurality of first wireless communication signals respectively during a first plurality of time periods associated respectively with a first plurality of symbols and also a plurality of first wireless sensing signals respectively during a second plurality of time periods associated respectively with a second plurality of symbols. Also, the method includes receiving, at the antenna device, a plurality of second wireless communication signals respectively during a third plurality of time periods associated respectively with a third plurality of symbols and also a plurality of second wireless sensing signals respectively during the second plurality of time periods. The second plurality of time periods are interleaved among respective pairs of the first plurality of time periods.

Abstract: Radar System The disclosure relates to a radar system having multiple radar transceiver modules, in which each module has a clock signal that is synchronised with a clock signal generated by a leader transceiver module.

Abstract: A radar device (100) is described that includes at least one transceiver (105) configured to support frequency modulated continuous wave (FMCW); radar device (100) and a digital controller (262). A temperature sensor system includes a plurality of temperature sensors (222, 232, 242) coupled to one or more circuits (220, 230, 240) in the at least one transceiver (105). The digital controller (262, 306) comprises or is operably coupled to an over-temperature emulation circuit (308) configured to emulate an over-temperature shutdown state by injecting an over-temperature force signal (290) into the temperature sensor system (270).

Abstract: A communication unit (300) is described that includes a plurality of cascaded devices that includes at least one master device and at least one slave device configured in a master-slave arrangement. The at least one master device comprises a modulator circuit (362) configured to: receive a system clock signal and a frame start signal; modulate the system clock signal with the frame start signal to produce a modulated master-slave clock signal (384); and transmit the modulated master-slave clock signal (384) to the at least one slave device. The at least one slave device comprises a demodulator circuit (364) configured to: receive and demodulate the modulated master-slave clock signal (384); and re-create therefrom the system clock signal (388, 385) and the frame start signal (390, 386).

Abstract: In accordance with a first aspect of the present disclosure, a radar unit is provided, comprising: a receiver circuit configured to receive a radar signal; a controller configured to control said receiver circuit, wherein said controller is configured to cause said receiver circuit to operate either in a complex receiver mode or in a real receiver mode. In accordance with a second aspect of the present disclosure, a method of operating a radar unit is conceived, comprising: receiving, by a receiver circuit comprised in the radar unit, a radar signal; controlling, by a controller comprised in said radar unit, said receiver circuit, wherein said controller causes said receiver circuit to operate either in a complex receiver mode or in a real receiver mode.

Abstract: The disclosure relates to a radar transceiver having a transmitter comprising a phase shifter.

Abstract: A radar system includes a hybrid-power amplifier and a power control unit coupled to the hybrid-power amplifier. The power control unit is configured to control the amplification of a chirp signal output by the radar system based upon an assessment of an interchirp time provided by a chirp profile. The interchirp time is a time difference between a first chirp signal and a second chirp signal that are to be output by the hybrid-power amplifier. When the power control unit determines that the interchirp time is less than an interchirp time threshold, a fast-power loop control configuration is used to control the transmitted output power at hybrid amplifier level. When the power control unit determines that the interchirp time is equal to or greater than the interchirp time threshold, a slow-power loop configuration or a combination of the slow-loop configuration and the fast-loop configuration is used to control the transmitted output power at the hybrid-power amplifier.

Abstract: The disclosure relates to apparatus and methods for self-testing of a duty cycle detector. Example embodiments include a circuit (201) comprising: a clock signal generator (205) configured to provide an output clock signal (203) having a duty cycle; a duty cycle detector (208) arranged to receive the output clock signal (203) and provide an output flag if the duty cycle of the clock signal (203) is outside a predetermined range; a controller (214) arranged to provide a duty cycle select signal (216) to the clock signal generator (205) to cause the clock signal (203) to have a duty cycle outside the predetermined range and to receive the output flag to confirm operation of the duty cycle detector (208).

Abstract: A chirp linearity detector, integrated circuit, and method are provided. The chirp linearity detector comprises a phase-locked loop (PLL) frequency sampling circuit and a frequency sweep linearity measuring circuit. The PLL frequency sampling circuit comprises a frequency divider circuit for receiving a PLL output signal from a PLL and for providing a frequency divided output signal, a first low pass filter circuit for receiving the frequency divided output signal, for reducing harmonic mixing, and for providing a mixer input signal, a mixer circuit for receiving the mixer input signal, for mixing the mixer input signal with a local oscillator signal, and for providing a mixer output signal, a second low pass filter circuit for performing anti-aliasing filtering and for providing an analog-to-digital converter (ADC) input signal, and an ADC circuit for digitizing the ADC input signal and for providing a digital output signal.

Abstract: A chirp linearity detector, integrated circuit, and method are provided. The chirp linearity detector comprises a phase-locked loop (PLL) frequency sampling circuit and a frequency sweep linearity measuring circuit. The PLL frequency sampling circuit comprises a frequency divider circuit for receiving a PLL output signal from a PLL and for providing a frequency divided output signal, a first low pass filter circuit for receiving the frequency divided output signal, for reducing harmonic mixing, and for providing a mixer input signal, a mixer circuit for receiving the mixer input signal, for mixing the mixer input signal with a local oscillator signal, and for providing a mixer output signal, a second low pass filter circuit for performing anti-aliasing filtering and for providing an analog-to-digital converter (ADC) input signal, and an ADC circuit for digitizing the ADC input signal and for providing a digital output signal.

Abstract: A fast chirp Phase Locked Loop with a boosted return time includes a Voltage Controlled Oscillator, VCO, generating a Frequency Modulated Continuous Waveform, FMCW. The VCO responds to a filtered output voltage of a filter connected to a charge pump. A digital controller modifies the FMCW to generate a chirp phase and a return phase. The chirp phase includes a first linear change of the FMCW from a start frequency to a stop frequency. The return phase includes a second linear change of the FMCW from the stop frequency to the start frequency. A boost circuit connects to the digital controller and the filter. The boost circuit supplies a boost current during the return phase. The boost current is proportional to a return slope of the return phase and inversely proportional to a VCO gain of the VCO.

Abstract: A fast chirp Phase Locked Loop with a phase preset includes a Voltage Controlled Oscillator, VCO, generating a Frequency Modulated Continuous Waveform, FMCW. The VCO responds to a filtered output voltage of a filter connected to a charge pump. A digital controller modifies the FMCW to generate a chirp phase and a return phase. The chirp phase includes a first linear change of the FMCW from a start frequency to a stop frequency. The return phase includes a second linear change of the FMCW from the stop frequency to the start frequency. A phase preset circuit connects to the digital controller and the filter. The phase preset circuit supplies a phase preset current during a start frequency time preceding the chirp phase. The phase preset current is proportional to a VCO gain of the VCO and inversely proportional to a chirp current during the chirp phase.