Abstract: One embodiment of the present invention provides a system that performs an efficient path-based static timing analysis (STA) in a circuit design. During operation, the system identifies a set of paths within the circuit design, wherein each path includes one or more segments. For a path in the set of paths, the system determines if at least one segment in the path is shared with a different path which was previously computed by performing a path-based STA, wherein the at least one segment in the different path is associated with previously computed path-based timing information. If so, the system then performs an estimation of a path-based delay for the path based at least on the path-based timing information associated with the shared segment in the different path. Otherwise, the system computes a path-based delay for the path by performing a path-based STA on the path.

Abstract: Methods and apparatus are provided for modeling and synthesizing circuits for packet processing that transform one or more fields of a packet. A circuit for packet processing that transforms one or more fields of a packet is modeled by representing the transformation using a packet editing graph having at least one node. The transformation can comprise one or more of adding, removing, modifying and maintaining the at least one field of a packet header. A circuit for packet processing that transforms one or more fields of a packet is synthesized by synthesizing a control finite state machine based on the packet editing graph, wherein the packet editing graph represents the circuit for packet processing. Elements of the packet editing graph are transformed in a predefined manner into corresponding elements of the synthesized circuit for packet processing.