Abstract: A machine for evaluating failing software programs, a non-transitory computer-readable storage medium with an error analysis program stored thereon and an error analysis program executed by a microprocessor are disclosed. In one embodiment a machine for investigating an error source in a software program includes a microprocessor coupled to a memory, wherein the microprocessor is programmed to determine whether a failure of an error-prone program step occurs reproducibly by providing the software program with the error-prone program step, executing program steps preceding the error-prone program step, executing the error-prone program step a number of times and calculating a failure probability for the error-prone program step.

Abstract: A method for measuring user perception quality of a processing system comprising a user interface is presented. The method comprises measuring a first processing time for processing, by the processing system, one or more times one or more operations in a batch mode; measuring a second processing time for processing, by the processing system, the one or more times the one or more operations and a predefined safety period in a user mode; and determining a user perception metric as a difference of a first value and a second value, the first value being determined depending on a ratio of the second processing time and the first processing time, the second value being determined depending on a ratio of the predefined safety period and the first processing time.

Abstract: A method of debugging software for an Integrated Development Environment connected to a target hardware system and to a simulator configured to simulate the target hardware system. The method comprises receiving, by a debugging tool of the Integrated Development Environment, simulator debugging data from the simulator, receiving, by the debugging tool, hardware debugging data from the target hardware system, comparing, by the debugging tool, the hardware debugging data with the simulator debugging data; and indicating, by the debugging tool, the result of comparing the hardware debugging data with the simulator debugging data.

Abstract: A machine and methods for reassign the execution order of program steps of a multi-step test program is disclosed. In an embodiment a machine for evaluating an error in a software program includes a microprocessor coupled to a memory, wherein the microprocessor is programmed to evaluate the error by (a) providing program steps of the software program, (b) assigning a position number to each program step, (c) performing an evaluation run on the program steps, (d) evaluating a performance of each program step, (e) rearranging the position number of each program step based on the performance of each program step, and (f) repeating steps (c)-(e).

Abstract: A machine and methods for reassign the execution order of program steps of a multi-step test program is disclosed. In an embodiment a machine for evaluating an error in a software program includes a microprocessor coupled to a memory, wherein the microprocessor is programmed to evaluate the error by (a) providing program steps of the software program, (b) assigning a position number to each program step, (c) performing an evaluation run on the program steps, (d) evaluating a performance of each program step, (e) rearranging the position number of each program step based on the performance of each program step, and (f) repeating steps (c)-(e).

Abstract: A machine for evaluating failing software programs, a non-transitory computer-readable storage medium with an error analysis program stored thereon and an error analysis program executed by a microprocessor are disclosed. In one embodiment a machine for investigating an error source in a software program includes a microprocessor coupled to a memory, wherein the microprocessor is programmed to determine whether a failure of an error-prone program step occurs reproducibly by providing the software program with the error-prone program step, executing program steps preceding the error-prone program step, executing the error-prone program step a number of times and calculating a failure probability for the error-prone program step.

Abstract: A method of debugging software for an Integrated Development Environment connected to a target hardware system and to a simulator configured to simulate the target hardware system. The method comprises receiving, by a debugging tool of the Integrated Development Environment, simulator debugging data from the simulator, receiving, by the debugging tool, hardware debugging data from the target hardware system, comparing, by the debugging tool, the hardware debugging data with the simulator debugging data; and indicating, by the debugging tool, the result of comparing the hardware debugging data with the simulator debugging data.

Abstract: A system comprises a test framework architecture for tree sequence testing of a device, comprising a plurality of hierarchical layers at least comprising an upmost layer and a lowest layer, each layer of the plurality of hierarchical layers comprising at least one of a plurality of test sequences, each test sequence comprising a plurality of test steps, each test step comprising a current layer information; a test action information for carrying out a test action on the device; and a recovery information for carrying out a recovery action on reception of a recovery call from a next lower layer.

Abstract: A system comprises a test framework architecture for tree sequence testing of a device, comprising a plurality of hierarchical layers at least comprising an upmost layer and a lowest layer, each layer of the plurality of hierarchical layers comprising at least one of a plurality of test sequences, each test sequence comprising a plurality of test steps, each test step comprising a current layer information; a test action information for carrying out a test action on the device; and a recovery information for carrying out a recovery action on reception of a recovery call from a next lower layer.