Abstract: An electronic device is proposed. The electronic device comprises: at least one electronic component formed in a chip of semiconductor material; at least one radioisotope power source unit comprising a radioactive material. The at least one radioisotope power source unit is embedded in the chip of semiconductor material together with the at least one electronic component. Moreover, the at least one radioisotope power source unit is arranged for providing electric power to said at least one electronic component by absorbing particles emitted by said radioactive material comprised in the least one radioisotope power source unit.

Abstract: An electronic device is proposed. The electronic device comprises: at least one electronic component formed in a chip of semiconductor material; at least one radioisotope power source unit comprising a radioactive material. The at least one radioisotope power source unit is embedded in the chip of semiconductor material together with the at least one electronic component. Moreover, the at least one radioisotope power source unit is arranged for providing electric power to said at least one electronic component by absorbing particles emitted by said radioactive material comprised in the least one radioisotope power source unit.

Abstract: Semiconductor device formed by a first conductive strip of semiconductor material; a control gate region of semiconductor material, facing a channel portion of the first conductive strip, and an insulation region arranged between the first conductive strip and the control gate region. The first conductive strip includes a conduction line having a first conductivity type and a control line having a second conductivity type, arranged adjacent and in electrical contact with each other, and the conduction line forms the channel portion, a first conduction portion and a second conduction portion arranged on opposite sides of the channel portion.

Abstract: Semiconductor device formed by a first conductive strip of semiconductor material; a control gate region of semiconductor material, facing a channel portion of the first conductive strip, and an insulation region arranged between the first conductive strip and the control gate region. The first conductive strip includes a conduction line having a first conductivity type and a control line having a second conductivity type, arranged adjacent and in electrical contact with each other, and the conduction line forms the channel portion, a first conduction portion and a second conduction portion arranged on opposite sides of the channel portion.

Abstract: Semiconductor device formed by a first conductive strip of semiconductor material; a control gate region of semiconductor material, facing a channel portion of the first conductive strip, and an insulation region arranged between the first conductive strip and the control gate region. The first conductive strip includes a conduction line having a first conductivity type and a control line having a second conductivity type, arranged adjacent and in electrical contact with each other, and the conduction line forms the channel portion, a first conduction portion and a second conduction portion arranged on opposite sides of the channel portion.

Abstract: Semiconductor device formed by a first conductive strip of semiconductor material; a control gate region of semiconductor material, facing a channel portion of the first conductive strip, and an insulation region arranged between the first conductive strip and the control gate region. The first conductive strip includes a conduction line having a first conductivity type and a control line having a second conductivity type, arranged adjacent and in electrical contact with each other, and the conduction line forms the channel portion, a first conduction portion and a second conduction portion arranged on opposite sides of the channel portion.

Abstract: A circuit generates a regulated voltage, in particular for gate terminals of non-volatile memory cells of the floating gate type. The circuit includes a generator circuit adapted to generate an unregulated voltage on its output. A comparator circuit is coupled to the output of the generator circuit including a reference element including a non-volatile memory cell of the floating gate type and adapted to output an error signal tied to the difference between the unregulated voltage and the threshold voltage of the cell. A regulator circuit is coupled to the output of the comparator circuit and is operative to regulate the unregulated voltage based on the value of the error signal. The regulated voltage is made programmable and tied to the parameters of the memory cell.

Abstract: In a storage device of the multi-level type, comprising a plurality of memory cells addressable through an address input each cell being adapted for storing more than one binary information element in a MOS transistor which has a control gate, and a floating gate for storing electrons to modify the threshold voltage of the transistor, and comprising a circuit enabling a Direct Memory Access (DMA) mode for directly accessing the memory cells from outside the device, the memory cells are programmed in the direct memory access mode by controlling, from outside the device, the amount of charge stored into the floating gate of each transistor.

Abstract: A timing circuit for reading from a device comprising multi-level non-volatile memory cells, which circuit comprises a single programmable delay block connected to an input terminal for memory address line transition signals. The delay block drives a counter which feedback controls the discharge through a combinational logic circuit connected to the output terminal of the programmable delay block. A logic output circuit, connected to the output terminal of the delay block and to the counter, generates the timing signals.

Abstract: A read circuit for semiconductor memory cells, comprising first and second active elements coupled to a supply line via at least a first switch, wherein the first and second active elements are respectively connected, at first and second circuit nodes, respectively, to a first transistor through which the active elements are coupled to a ground. These first and second circuit nodes are also connected to ground through first and second capacitive elements, respectively, each having a switch connected in parallel to the capacitive element.

Abstract: A read circuit for semiconductor memory cells, comprising first and second active elements coupled to a supply line via at least a first switch, wherein the first and second active elements are respectively connected, at first and second circuit nodes, respectively, to a first transistor through which the active elements are coupled to a ground. These first and second circuit nodes are also connected to ground through first and second capacitive elements, respectively, each having a switch connected in parallel to the capacitive element.

Abstract: Reading circuit for multilevel non-volatile memory cell devices having, for each cell to be read, a selection line with which is associated a load and a decoupling and control stage with a feedback loop which stabilizes the voltage on a circuit node of the selection line. To this node are connected a current replica circuit which are controlled by the feedback loop. These include loads and circuit elements homologous to those associated with the selection line of the memory cell and have an output interface circuit for connection to current comparator circuit.

Abstract: A voltage step-up circuit with regulated output voltage, comprises a voltage divider and a current-absorption circuit connected between the output terminal of the circuit and ground. A control circuit connected to the divider drives the switching of the current-absorption circuit.

Abstract: A page-mode semiconductor memory device comprises a matrix of memory cells arranged in rows and columns, each row forming a memory page of the memory device and comprising at least one group of memory cells, memory page selection means for selecting a row of the matrix, and a plurality of sensing circuits each one associated with a respective column of the matrix. The memory cells are multiple-level memory cells which can be programmed in a plurality of c=2b(b>1) programming states to store b information bits, and the sensing circuits are serial-dichotomic sensing circuits capable of determining, in a number b of consecutive approximation steps, the b information bits stored in the memory cells, at each step one of said b information bits being determined, said at least one group of memory cells of a row forming a number b of memory words of a memory page.

Abstract: A method for sensing multiple-levels non-volatile memory cells which can take one programming level among a plurality of m=2.sup.n (n>=Z) different programming levels, provides for biasing a memory cell to be sensed in a predetermined condition, so that the memory cell sinks a cell current with a value belonging to a discrete set of m distinct cell current values, each cell current value corresponding to one of said programming levels.

Abstract: A read circuit for memory cells which has two legs, each having, in cascade with one another, an electronic switch (SW1,SW2), an active element (T1,T2), feedback connected to the active element in the other leg to jointly produce a voltage amplifier, and a switch load element (L1,L2). Each active element is driven through a high-impedance input circuit element.

Abstract: A serial dichotomic method for sensing multiple-level non-volatile memory cells which can take one of m=2.sup.n (n>=2) different programming levels, provides for biasing a memory cell to be sensed in a predetermined condition, so that the memory cell sinks a cell current with a value belonging to a plurality of m distinct cell current values, and for: a) comparing the cell current with a reference current which has a value comprised between a minimum value and a maximum value of said plurality of m cell current values, thus dividing said plurality of cell current values into two sub-pluralities of cell current values, and determining the sub-plurality of cell current values to which the cell current belongs; b) repeating the step a) until the sub-plurality of cell current values to which the cell current belongs comprises only one cell current value, which is the value for the current of the memory cell to be sensed.

Abstract: A device for reading memory cells, wherein the device contains two branches, wherein each branch comprises, connected in cascade, an electronic switch, an active element reactively connected to the active element of the other branch, so as to form a voltage amplifier. Each active element is controlled by means of a high impedance circuit element. A microswitch connects the two branches together is inserted between the two active elements.

Abstract: A sensing circuit for serial dichotomic sensing of multiple-level memory cells which can take one programming level among a plurality of m=2.sup.n (n>=2) different programming levels, comprises biasing means for biasing a memory cell to be sensed in a predetermined condition, so that the memory cell sinks a cell current with a value belonging to a plurality of m distinct cell current values, each cell current value corresponding to one of the programming levels, a current comparator for comparing the cell current with a reference current generated by a variable reference current generator, and a successive approximation register supplied with an output signal of the current comparator and controlling the variable reference current generator.

Abstract: A sensing circuit for serial dichotomic sensing of multiple-level memory cells which can take one programming level among a plurality of m=2n (n>=2) different programming levels, comprises biasing means for biasing a memory cell to be sensed in a predetermined condition, so that the memory cell sinks a cell current with a value belonging to a plurality of m distinct cell current values, each cell current value corresponding to one of the programming levels, a current comparator for comparing the cell current with a reference current generated by a variable reference current generator, and a successive approximation register supplied with an output signal of the current comparator and controlling the variable reference current generator.