Abstract: In some implementations, a memory device may receive a command to read data in a first format from non-volatile memory, the data being stored in a second format in the non-volatile memory, the second format comprising a plurality of copies of the data in the first format. The memory device may compare, using an error correction circuit, the plurality of copies of the data to determine a dominant bit state for bits of the data. The memory device may store the dominant bit state for bits of the data in the non-volatile memory as error-corrected data in the first format. The memory device may cause the error-corrected data to be read from the non-volatile memory in the first format as a response to the command to read the data in the first format.

Abstract: Embodiments of the present disclosure may relate to a memory controller that may include a main controller to begin a power down of a non-volatile memory storage during a first time period, while operating in a first voltage range, wherein the main controller is to begin the power down of the non-volatile memory in response to an indication of a voltage level being below a predetermined threshold; and a sequencer to continue the power down of the memory storage during a second time period, while operating within a second voltage range lower than the first voltage range. In some embodiments, the sequencer may include a state machine to perform a discharge sequence, where the state machine includes a micro-action output to output a micro-action command to the memory storage based at least in part on a current state of the state machine. Other embodiments may be described and/or claimed.

Abstract: Embodiments of the present disclosure may relate to a memory controller that may include a main controller to begin a power down of a non-volatile memory storage during a first time period, while operating in a first voltage range, wherein the main controller is to begin the power down of the non-volatile memory in response to an indication of a voltage level being below a predetermined threshold; and a sequencer to continue the power down of the memory storage during a second time period, while operating within a second voltage range lower than the first voltage range. In some embodiments, the sequencer may include a state machine to perform a discharge sequence, where the state machine includes a micro-action output to output a micro-action command to the memory storage based at least in part on a current state of the state machine. Other embodiments may be described and/or claimed.

Abstract: A non-volatile, integrated circuit memory, such as a Flash EPROM, including an array 1 of memory cells 10, each cell having a floating gate 14 for programming the cell and a control gate 11 for reading the cell, the array having a plurality of row lines 15, a plurality of column lines 25 and a plurality of output lines 18. Included is a decoder circuit 16 having a plurality of input lines 94, 96, for each row in the array, and having as outputs the row lines 15. The decoder circuit includes a decoder logic circuit associated with each row line, the decoder logic circuit including a plurality of low power logic devices 84-90 interconnected to perform a predetermined decoding function on the signals on the input lines for the associated row line to apply a signal to an associated row node when the decoder logic circuit determines that the associated row line is selected.

Abstract: A method and apparatus for recognizing a script written character wherein the character is entered using character entering means and digitised by appropriate means. The digitised character is then stored in, for example, a memory. Codes representing topological and vector features of the character are extracted from the character, then the topological and vector features of the character are compared with topological and vector features of a plurality of reference characters defining a set of reference characters stored in a memory. Each of the reference characters included in the set corresponds to a specific script written character. A logic process is then performed to determine which reference character of the set of reference characters has topological and vector features most closely corresponding to the topological and vector features of the digitized character thereby identifying the script written character.

Abstract: A method for selectibly erasing one or more non-volatile programmable memory cells in an integrated circuit. The method is applicable to an array 1 of memory cells 10 fabricated in a semiconductor substrate 30 of a first conductivity type semiconductor material, each cell having a floating gate 14 for programming the cell and a control gate 11 for reading the cell, the array having a plurality of row lines 15, a plurality of column lines 25 and a plurality of output lines 18. The cells should be formed in a first well 33 of said first conductivity type semiconductor material, the first wells being formed in second wells 31 of a second conductivity type semiconductor material, the first wells including cells in groups of one or more. The method involves the steps of applying a high voltage source to a selected one or more column lines, applying a zero voltage source to a selected one or more row lines; and applying the high voltage source to non-selected row lines.

Abstract: A method for automatically detecting and correcting the underprogramming of a memory cell 10 in a non-volatile, progrommable memory array 1, the array having a plurality of such cells, each such cell being programmable by a progromming step that stores charge therein and being erasable by an erasing step that removes charge therefrom, and each such cell being readable to determine whether such cell is in a progrommed state or in an erased state. First, charge is stored in a selected cell therein 74. Then the selected cell is read to determine whether the selected cell is programmed 78. If the step of reading does not determine such cell to be programmed 80, the steps of storing and reading are automatically repeated until either the step of sensing indicates a sufficiently programmed cell or, alternatively, until a predermined number of iterations of the steps has been performed 86.

Abstract: This invention relates to a method and apparatus for recognizing a script written character. The character is entered using character entering device and digitised by appropriate device. The digitised character is then stored in, for example, a memory. Codes representing topological, vector dimension features and the microfeatures of the character are extracted from the character, then the features of the character are compared with a set of reference features corresponding thereto stored in a memory. Each of the set of reference characters corresponding with a specific script written character. A logic process is then performed to determine which of the set of reference features most closely corresponds to the topological features of the digitized character thereby identifying the script written character. The relative weighting of the feature can be varied for different types of script or confusing characters to enable still more accurate recognition.