Patents by Inventor Cristina SOMMA

Cristina SOMMA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240145364
    Abstract: A BGA package includes an array of electrically conductive balls providing electrical contact for a semiconductor die. A power channel is provided to convey power supply current towards the semiconductor die. The power channel is formed by a stack of electrically conductive planes. The electrically conductive planes are stacked in a stepped arrangement wherein a number of stacked planes in each step of the stack increases in a direction from a distal end to a proximal end of the power channel. Adjacent electrically conductive planes in the stack of the power channel are electrically coupled with electrically conductive vias extending therebetween. Current conduction paths towards the die area thus have resistance values that decrease from the distal end to the proximal end of the power channel.
    Type: Application
    Filed: November 1, 2023
    Publication date: May 2, 2024
    Applicant: STMicroelectronics S.r.l.
    Inventors: Aurora SANNA, Cristina SOMMA, Damian HALICKI
  • Publication number: 20240096759
    Abstract: One or more embodiments are directed to quad flat no-lead (QFN) semiconductor packages, devices, and methods in which one or more electrical components are positioned between a die pad of a QFN leadframe and a semiconductor die. In one embodiment, a device includes a die pad, a lead that is spaced apart from the die pad, and at least one electrical component that has a first contact on the die pad and a second contact on the lead. A semiconductor die is positioned on the at least one electrical component and is spaced apart from the die pad by the at least one electrical component. The device further includes at least one conductive wire, or wire bond, that electrically couples the at least one lead to the semiconductor die.
    Type: Application
    Filed: November 13, 2023
    Publication date: March 21, 2024
    Applicant: STMICROELECTRONICS S.r.l.
    Inventors: Cristina SOMMA, Fulvio Vittorio FONTANA
  • Patent number: 11842948
    Abstract: One or more embodiments are directed to quad flat no-lead (QFN) semiconductor packages, devices, and methods in which one or more electrical components are positioned between a die pad of a QFN leadframe and a semiconductor die. In one embodiment, a device includes a die pad, a lead that is spaced apart from the die pad, and at least one electrical component that has a first contact on the die pad and a second contact on the lead. A semiconductor die is positioned on the at least one electrical component and is spaced apart from the die pad by the at least one electrical component. The device further includes at least one conductive wire, or wire bond, that electrically couples the at least one lead to the semiconductor die.
    Type: Grant
    Filed: April 29, 2021
    Date of Patent: December 12, 2023
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Cristina Somma, Fulvio Vittorio Fontana
  • Patent number: 11810839
    Abstract: One or more embodiments are directed to semiconductor packages and methods in which one or more electrical components are positioned between a semiconductor die and a surface of a substrate. In one embodiment, a semiconductor package includes a substrate having a first surface. One or more electrical components are electrically coupled to electrical contacts on the first surface of the substrate. A semiconductor die is positioned on the one or more electrical components, and the semiconductor die has an active surface that faces away from the substrate. An adhesive layer is on the first surface of the substrate and on the one or more electrical components, and the semiconductor die is spaced apart from the one or more electrical components by the adhesive layer. Wire bonds are provided that electrically couples the active surface of the semiconductor die to the substrate.
    Type: Grant
    Filed: February 17, 2022
    Date of Patent: November 7, 2023
    Assignee: STMICROELECTRONICS S.r.l.
    Inventor: Cristina Somma
  • Patent number: 11705388
    Abstract: A first device includes a rectangular substrate having a first width and a first length and a first pattern of electrical interface nodes at first, second and third sides with a first set of electrical interface nodes at the fourth side. A second device includes a second rectangular substrate having a second width equal to the first width, a second length and a median line extending in the direction of the second width. A second pattern of electrical interface nodes for the second device includes two unmorphed replicas of the first pattern arranged mutually rotated 180° on opposite sides of the median line as well as two second sets of electrical interface nodes formed by two smaller morphed replicas of the first set of electrical interface nodes arranged mutually rotated 180° on opposite sides of said median line.
    Type: Grant
    Filed: December 1, 2020
    Date of Patent: July 18, 2023
    Assignee: STMicroelectronics S.r.l.
    Inventors: Cristina Somma, Giovanni Graziosi
  • Publication number: 20220173018
    Abstract: One or more embodiments are directed to semiconductor packages and methods in which one or more electrical components are positioned between a semiconductor die and a surface of a substrate. In one embodiment, a semiconductor package includes a substrate having a first surface. One or more electrical components are electrically coupled to electrical contacts on the first surface of the substrate. A semiconductor die is positioned on the one or more electrical components, and the semiconductor die has an active surface that faces away from the substrate. An adhesive layer is on the first surface of the substrate and on the one or more electrical components, and the semiconductor die is spaced apart from the one or more electrical components by the adhesive layer. Wire bonds are provided that electrically couples the active surface of the semiconductor die to the substrate.
    Type: Application
    Filed: February 17, 2022
    Publication date: June 2, 2022
    Applicant: STMICROELECTRONICS S.r.l.
    Inventor: Cristina SOMMA
  • Publication number: 20220173064
    Abstract: A semiconductor die is mounted at a die area of a ball grid array package that includes an array of electrically-conductive ball. A power channel conveys a power supply current to the semiconductor die. The power channel is formed by an electrically-conductive connection plane layers extending in a longitudinal direction between a distal end at a periphery of the package and a proximal end at the die area. A distribution of said electrically-conductive balls is made along the longitudinal direction. The electrically-conductive connection plane layer includes subsequent portions in the longitudinal direction between adjacent electrically-conductive balls of the distribution. Respective electrical resistance values of the subsequent portions monotonously decrease from the distal end to the proximal end. A uniform distribution of power supply current over the length of the power channel is thus facilitated.
    Type: Application
    Filed: November 29, 2021
    Publication date: June 2, 2022
    Applicant: STMicroelectronics S.r.l.
    Inventors: Cristina SOMMA, Aurora SANNA, Damian HALICKI
  • Patent number: 11276628
    Abstract: One or more embodiments are directed to semiconductor packages and methods in which one or more electrical components are positioned between a semiconductor die and a surface of a substrate. In one embodiment, a semiconductor package includes a substrate having a first surface. One or more electrical components are electrically coupled to electrical contacts on the first surface of the substrate. A semiconductor die is positioned on the one or more electrical components, and the semiconductor die has an active surface that faces away from the substrate. An adhesive layer is on the first surface of the substrate and on the one or more electrical components, and the semiconductor die is spaced apart from the one or more electrical components by the adhesive layer. Wire bonds are provided that electrically couples the active surface of the semiconductor die to the substrate.
    Type: Grant
    Filed: March 19, 2020
    Date of Patent: March 15, 2022
    Assignee: STMICROELECTRONICS S.r.l.
    Inventor: Cristina Somma
  • Publication number: 20210249337
    Abstract: One or more embodiments are directed to quad flat no-lead (QFN) semiconductor packages, devices, and methods in which one or more electrical components are positioned between a die pad of a QFN leadframe and a semiconductor die. In one embodiment, a device includes a die pad, a lead that is spaced apart from the die pad, and at least one electrical component that has a first contact on the die pad and a second contact on the lead. A semiconductor die is positioned on the at least one electrical component and is spaced apart from the die pad by the at least one electrical component. The device further includes at least one conductive wire, or wire bond, that electrically couples the at least one lead to the semiconductor die.
    Type: Application
    Filed: April 29, 2021
    Publication date: August 12, 2021
    Applicant: STMICROELECTRONICS S.R.L.
    Inventors: Cristina SOMMA, Fulvio Vittorio FONTANA
  • Publication number: 20210167029
    Abstract: A first device includes a rectangular substrate having a first width and a first length and a first pattern of electrical interface nodes at first, second and third sides with a first set of electrical interface nodes at the fourth side. A second device includes a second rectangular substrate having a second width equal to the first width, a second length and a median line extending in the direction of the second width. A second pattern of electrical interface nodes for the second device includes two unmorphed replicas of the first pattern arranged mutually rotated 180° on opposite sides of the median line as well as two second sets of electrical interface nodes formed by two smaller morphed replicas of the first set of electrical interface nodes arranged mutually rotated 180° on opposite sides of said median line.
    Type: Application
    Filed: December 1, 2020
    Publication date: June 3, 2021
    Applicant: STMicroelectronics S.r.l.
    Inventors: Cristina SOMMA, Giovanni GRAZIOSI
  • Patent number: 11004775
    Abstract: One or more embodiments are directed to quad flat no-lead (QFN) semiconductor packages, devices, and methods in which one or more electrical components are positioned between a die pad of a QFN leadframe and a semiconductor die. In one embodiment, a device includes a die pad, a lead that is spaced apart from the die pad, and at least one electrical component that has a first contact on the die pad and a second contact on the lead. A semiconductor die is positioned on the at least one electrical component and is spaced apart from the die pad by the at least one electrical component. The device further includes at least one conductive wire, or wire bond, that electrically couples the at least one lead to the semiconductor die.
    Type: Grant
    Filed: February 5, 2020
    Date of Patent: May 11, 2021
    Assignee: STMICROELECTRONICS S.r.l.
    Inventors: Cristina Somma, Fulvio Vittorio Fontana
  • Publication number: 20200219799
    Abstract: One or more embodiments are directed to semiconductor packages and methods in which one or more electrical components are positioned between a semiconductor die and a surface of a substrate. In one embodiment, a semiconductor package includes a substrate having a first surface. One or more electrical components are electrically coupled to electrical contacts on the first surface of the substrate. A semiconductor die is positioned on the one or more electrical components, and the semiconductor die has an active surface that faces away from the substrate. An adhesive layer is on the first surface of the substrate and on the one or more electrical components, and the semiconductor die is spaced apart from the one or more electrical components by the adhesive layer. Wire bonds are provided that electrically couples the active surface of the semiconductor die to the substrate.
    Type: Application
    Filed: March 19, 2020
    Publication date: July 9, 2020
    Inventor: Cristina SOMMA
  • Publication number: 20200176363
    Abstract: One or more embodiments are directed to quad flat no-lead (QFN) semiconductor packages, devices, and methods in which one or more electrical components are positioned between a die pad of a QFN leadframe and a semiconductor die. In one embodiment, a device includes a die pad, a lead that is spaced apart from the die pad, and at least one electrical component that has a first contact on the die pad and a second contact on the lead. A semiconductor die is positioned on the at least one electrical component and is spaced apart from the die pad by the at least one electrical component. The device further includes at least one conductive wire, or wire bond, that electrically couples the at least one lead to the semiconductor die.
    Type: Application
    Filed: February 5, 2020
    Publication date: June 4, 2020
    Inventors: Cristina SOMMA, Fulvio Vittorio FONTANA
  • Patent number: 10593612
    Abstract: One or more embodiments are directed to quad flat no-lead (QFN) semiconductor packages, devices, and methods in which one or more electrical components are positioned between a die pad of a QFN leadframe and a semiconductor die. In one embodiment, a device includes a die pad, a lead that is spaced apart from the die pad, and at least one electrical component that has a first contact on the die pad and a second contact on the lead. A semiconductor die is positioned on the at least one electrical component and is spaced apart from the die pad by the at least one electrical component. The device further includes at least one conductive wire, or wire bond, that electrically couples the at least one lead to the semiconductor die.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: March 17, 2020
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Cristina Somma, Fulvio Vittorio Fontana
  • Publication number: 20190287880
    Abstract: One or more embodiments are directed to quad flat no-lead (QFN) semiconductor packages, devices, and methods in which one or more electrical components are positioned between a die pad of a QFN leadframe and a semiconductor die. In one embodiment, a device includes a die pad, a lead that is spaced apart from the die pad, and at least one electrical component that has a first contact on the die pad and a second contact on the lead. A semiconductor die is positioned on the at least one electrical component and is spaced apart from the die pad by the at least one electrical component. The device further includes at least one conductive wire, or wire bond, that electrically couples the at least one lead to the semiconductor die.
    Type: Application
    Filed: March 19, 2018
    Publication date: September 19, 2019
    Inventors: Cristina SOMMA, Fulvio Vittorio FONTANA
  • Publication number: 20190287881
    Abstract: One or more embodiments are directed to semiconductor packages and methods in which one or more electrical components are positioned between a semiconductor die and a surface of a substrate. In one embodiment, a semiconductor package includes a substrate having a first surface. One or more electrical components are electrically coupled to electrical contacts on the first surface of the substrate. A semiconductor die is positioned on the one or more electrical components, and the semiconductor die has an active surface that faces away from the substrate. An adhesive layer is on the first surface of the substrate and on the one or more electrical components, and the semiconductor die is spaced apart from the one or more electrical components by the adhesive layer. Wire bonds are provided that electrically couples the active surface of the semiconductor die to the substrate.
    Type: Application
    Filed: March 19, 2018
    Publication date: September 19, 2019
    Inventor: Cristina SOMMA