Patents by Inventor Cristinel Zonte
Cristinel Zonte has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11940831Abstract: In accordance with an embodiment, a circuit includes: a trimmable reference current generator having a temperature dependent current output node, the trimmable reference current generator including: a proportional to absolute temperature (PTAT) current generation circuit; a first programmable current scaling circuit coupled to the PTAT current generation circuit and including a first output coupled to the temperature dependent current output node; a constant current generation circuit; a second programmable current scaling circuit coupled to the constant current generation circuit and including a first output coupled to the temperature dependent current output node; and a reference interface circuit having an input coupled to the temperature dependent current output node and an output configured to be coupled to a reference current input of a memory sense amplifier.Type: GrantFiled: March 3, 2022Date of Patent: March 26, 2024Assignee: Infineon Technologies LLCInventor: Cristinel Zonte
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Publication number: 20230197128Abstract: Systems and methods for driving a non-volatile memory device in a standby operating condition are disclosed. A standby detection circuit detects whether the non-volatile memory system is in a standby condition. In response to determining that the non-volatile memory system is in a standby condition, a bias control circuit provides bias currents to drivers of the non-volatile memory system in a standby mode.Type: ApplicationFiled: February 13, 2023Publication date: June 22, 2023Inventors: Cristinel Zonte, Vijay Raghavan, Iulian C Gradinariu, Gary Peter Moscaluk, Roger Bettman, Vineet Argrawal, Samuel Leshner
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Publication number: 20230176604Abstract: In accordance with an embodiment, a circuit includes: a trimmable reference current generator having a temperature dependent current output node, the trimmable reference current generator including: a proportional to absolute temperature (PTAT) current generation circuit; a first programmable current scaling circuit coupled to the PTAT current generation circuit and including a first output coupled to the temperature dependent current output node; a constant current generation circuit; a second programmable current scaling circuit coupled to the constant current generation circuit and including a first output coupled to the temperature dependent current output node; and a reference interface circuit having an input coupled to the temperature dependent current output node and an output configured to be coupled to a reference current input of a memory sense amplifier.Type: ApplicationFiled: March 3, 2022Publication date: June 8, 2023Inventor: Cristinel Zonte
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Patent number: 11581029Abstract: Systems and methods for driving a non-volatile memory device in a standby operating condition are disclosed. A standby detection circuit detects whether the non-volatile memory system is in a standby condition. In response to determining that the non-volatile memory system is in a standby condition, a bias control circuit provides bias currents to drivers of the non-volatile memory system in a standby mode.Type: GrantFiled: April 30, 2021Date of Patent: February 14, 2023Assignee: LONGITUDE ELASH MEMORY SOLUTIONS LTDInventors: Cristinel Zonte, Vijay Raghavan, Iulian C Gradinariu, Gary Peter Moscaluk, Roger Bettman, Vineet Argrawal, Samuel Leshner
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Publication number: 20210327477Abstract: Systems and methods for driving a non-volatile memory device in a standby operating condition are disclosed. A standby detection circuit detects whether the non-volatile memory system is in a standby condition. In response to determining that the non-volatile memory system is in a standby condition, a bias control circuit provides bias currents to drivers of the non-volatile memory system in a standby mode.Type: ApplicationFiled: April 30, 2021Publication date: October 21, 2021Inventors: Cristinel Zonte, Vijay Raghavan, Iulian C. Gradinariu, Gary Peter Moscaluk, Roger Bettman, Vineet Argrawal, Samuel Leshner
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Patent number: 10998019Abstract: Systems and methods for driving a non-volatile memory device in a standby operating condition are disclosed. A standby detection circuit detects whether the non-volatile memory system is in a standby condition. In response to determining that the non-volatile memory system is in a standby condition, a bias control circuit provides bias currents to drivers of the non-volatile memory system in a standby mode.Type: GrantFiled: December 16, 2019Date of Patent: May 4, 2021Assignee: Longitude Flash Memory Solutions, Ltd.Inventors: Cristinel Zonte, Vijay Raghavan, Iulian C. Gradinariu, Gary Peter Moscaluk, Roger Bettman, Vineet Argrawal, Samuel Leshner
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Publication number: 20200234746Abstract: Systems and methods for driving a non-volatile memory device in a standby operating condition are disclosed. A standby detection circuit detects whether the non-volatile memory system is in a standby condition. In response to determining that the non-volatile memory system is in a standby condition, a bias control circuit provides bias currents to drivers of the non-volatile memory system in a standby mode.Type: ApplicationFiled: December 16, 2019Publication date: July 23, 2020Inventors: Cristinel Zonte, Vijay Raghavan, Iulian C. Gradinariu, Gary Peter Moscaluk, Roger Bettman, Vineet Argrawal, Samuel Leshner
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Patent number: 10510387Abstract: A method for driving a non-volatile memory system is disclosed. A standby detection circuit detects whether the nonvolatile memory system is in a standby condition. In response to determining that the non-volatile memory system is in a standby condition, a bias control circuit reduces bias currents provided to drivers of the non-volatile memory system in a standby mode. The non-volatile memory system is operated in the standby mode after the bias currents have been reduced, where an output signal indicating the standby mode is maintained until a read instruction is detected.Type: GrantFiled: August 6, 2018Date of Patent: December 17, 2019Assignee: LONGITUDE FLASH MEMORY SOLUTIONS LTD.Inventors: Cristinel Zonte, Vijay Raghavan, Iulian Gradinariu, Gary Peter Moscaluk, Roger Jay Bettman, Vineet Argrawal, Samuel Leshner
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Publication number: 20190080732Abstract: A method for driving a non-volatile memory system is disclosed. A standby detection circuit detects whether the nonvolatile memory system is in a standby condition. In response to determining that the non-volatile memory system is in a standby condition, a bias control circuit reduces bias currents provided to drivers of the non-volatile memory system in a standby mode. The non-volatile memory system is operated in the standby mode after the bias currents have been reduced, where an output signal indicating the standby mode is maintained until a read instruction is detected.Type: ApplicationFiled: August 6, 2018Publication date: March 14, 2019Applicant: Cypress Semiconductor CorporationInventors: Cristinel Zonte, Vijay Raghavan, Iulian Gradinariu, Gary Peter Moscaluk, Roger Jay Bettman, Vineet Argrawal, Samuel Leshner
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Patent number: 10062423Abstract: Systems and methods for driving a non-volatile memory device in a standby operating condition are disclosed. A standby detection circuit detects whether the non-volatile memory system is in a standby condition. In response to determining that the non-volatile memory system is in a standby condition, a bias control circuit provides bias currents to drivers of the non-volatile memory system in a standby mode.Type: GrantFiled: September 16, 2016Date of Patent: August 28, 2018Assignee: Cypress Semiconductor CorporationInventors: Cristinel Zonte, Vijay Raghavan, Iulian C. Gradinariu, Gary Peter Moscaluk, Roger Bettman, Vineet Argrawal, Samuel Leshner
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Patent number: 10032517Abstract: A system including a memory architecture is described. In one embodiment, the memory architecture includes an array of non-volatile memory cells, a first independently controlled voltage generation circuit, a plurality of register bits to store programmable values used by the independently controlled voltage generation circuit and a control circuit coupled to the first independently controlled voltage generation circuit. The first independently controlled voltage generation circuit is coupled to supply a positive voltage to the array during program and erase operations so that a magnitude of the positive voltage is applied across a storage note of an accessed memory cell of the array. The plurality of register bits to store programmable values used by the independently controlled voltage generation circuit to control the magnitude of the positive voltage. The control circuit controls a duration of the positive voltage. Other embodiments are also described.Type: GrantFiled: April 15, 2015Date of Patent: July 24, 2018Assignee: Cypress Semiconductor CorporationInventors: Ryan Tasuo Hirose, Fredrick B. Jenne, Vijay Raghavan, Igor G. Kouznetsov, Paul Fredrick Ruths, Cristinel Zonte, Bogdan I. Georgescu, Leonard Vasile Gitlan, James Paul Myers
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Publication number: 20180166140Abstract: A system including a memory architecture is described. In one embodiment, the memory architecture includes an array of non-volatile memory cells, a first independently controlled voltage generation circuit, a plurality of register bits to store programmable values used by the independently controlled voltage generation circuit and a control circuit coupled to the first independently controlled voltage generation circuit. The first independently controlled voltage generation circuit is coupled to supply a positive voltage to the array during program and erase operations so that a magnitude of the positive voltage is applied across a storage note of an accessed memory cell of the array. The plurality of register bits to store programmable values used by the independently controlled voltage generation circuit to control the magnitude of the positive voltage. The control circuit controls a duration of the positive voltage. Other embodiments are also described.Type: ApplicationFiled: April 15, 2015Publication date: June 14, 2018Inventors: Ryan Tasuo Hirose, Fredrick B. Jenne, Vijay Raghavan, Igor G. Kouznetsov, Paul Fredrick Ruths, Cristinel Zonte, Bogdan I. Georgescu, Leonard Vasile Gitlan, James Paul Myers
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Patent number: 9899089Abstract: A system including a memory architecture is described. In one embodiment, the memory architecture includes an array of non-volatile memory cells, a first independently controlled voltage generation circuit, a plurality of register bits to store programmable values used by the independently controlled voltage generation circuit and a control circuit coupled to the first independently controlled voltage generation circuit. The first independently controlled voltage generation circuit is coupled to supply a positive voltage to the array during program and erase operations so that a magnitude of the positive voltage is applied across a storage node of an accessed memory cell of the array. The plurality of register bits to store programmable values used by the independently controlled voltage generation circuit to control the magnitude of the positive voltage. The control circuit controls a duration of the positive voltage. Other embodiments are also described.Type: GrantFiled: September 24, 2013Date of Patent: February 20, 2018Assignee: Cypress Semiconductor CorporationInventors: Ryan Tasuo Hirose, Fredrick B. Jenne, Vijay Raghavan, Igor G. Kouznetsov, Paul Fredrick Ruths, Cristinel Zonte, Bogdan I. Georgescu, Leonard Vasile Gitlan, James Paul Myers
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Publication number: 20170098468Abstract: Systems and methods for driving a non-volatile memory device in a standby operating condition are disclosed. A standby detection circuit detects whether the non-volatile memory system is in a standby condition. In response to determining that the non-volatile memory system is in a standby condition, a bias control circuit provides bias currents to drivers of the non-volatile memory system in a standby mode.Type: ApplicationFiled: September 16, 2016Publication date: April 6, 2017Inventors: Cristinel Zonte, Vijay Raghavan, Iulian C. Gradinariu, Gary Peter Moscaluk, Roger Bettman, Vineet Argrawal, Samuel Leshner
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Patent number: 9595332Abstract: A circuit includes a first word line coupled to a non-volatile memory (NVM) cell. A first path includes a first inverter and a transistor. The transistor is coupled to the word line. The first path is coupled to receive a first input voltage signal. A second path includes at least the transistor coupled to the word line. At least a portion of the second path is embedded within the first path. The second path is coupled to receive a second input voltage signal.Type: GrantFiled: September 18, 2015Date of Patent: March 14, 2017Assignee: CYPRESS SEMICONDUCTOR CORPORATIONInventors: Bogdan Georgescu, Cristinel Zonte, Vijay Raghavan
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Publication number: 20160365147Abstract: A circuit includes a first word line coupled to a non-volatile memory (NVM) cell. A first path includes a first inverter and a transistor. The transistor is coupled to the word line. The first path is coupled to receive a first input voltage signal. A second path includes at least the transistor coupled to the word line. At least a portion of the second path is embedded within the first path. The second path is coupled to receive a second input voltage signal.Type: ApplicationFiled: September 18, 2015Publication date: December 15, 2016Inventors: Bogdan Georgescu, Cristinel Zonte, Vijay Raghavan
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Patent number: 9449655Abstract: Systems and methods for driving a non-volatile memory device in a standby operating condition are disclosed. A standby detection circuit detects whether the non-volatile memory system is in a standby condition. In response to determining that the non-volatile memory system is in a standby condition, a bias control circuit provides bias currents to drivers of the non-volatile memory system in a standby mode.Type: GrantFiled: December 11, 2015Date of Patent: September 20, 2016Assignee: Cypress Semiconductor CorporationInventors: Cristinel Zonte, Vijay Raghavan, Iulian C. Gradinariu, Gary Peter Moscaluk, Roger Bettman, Vineet Argrawal, Samuel Leshner
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Publication number: 20160005475Abstract: A system including a memory architecture is described. In one embodiment, the memory architecture includes an array of non-volatile memory cells, a first independently controlled voltage generation circuit, a plurality of register bits to store programmable values used by the independently controlled voltage generation circuit and a control circuit coupled to the first independently controlled voltage generation circuit. The first independently controlled voltage generation circuit is coupled to supply a positive voltage to the array during program and erase operations so that a magnitude of the positive voltage is applied across a storage note of an accessed memory cell of the array. The plurality of register bits to store programmable values used by the independently controlled voltage generation circuit to control the magnitude of the positive voltage. The control circuit controls a duration of the positive voltage. Other embodiments are also described.Type: ApplicationFiled: April 15, 2015Publication date: January 7, 2016Inventors: Ryan Tasuo Hirose, Fredrick B. Jenne, Vijay Raghavan, Igor G. Kouznetsov, Paul Fredrick Ruths, Cristinel Zonte, Bogdan I. Georgescu, Leonard Vasile Gitlan, James Paul Myers
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Patent number: 8908438Abstract: Flash memory devices and systems are provided. One flash memory device includes an n-channel metal oxide semiconductor field-effect transistor (nMOSFET), a silicon-oxide-nitride-oxide silicon (SONOS) transistor coupled to the nMOSFET, and an isolated p-well coupled to the nMOSFET and the SONOS transistor. A flash memory system includes an array of memory devices divided into a plurality of paired sectors, a global bit line (GBL) configured to provide high voltage to each respective sector during erase and program operations coupled to each of the plurality of sectors, and a plurality of sense amplifiers coupled between a respective pair of sectors. Methods for operating a flash memory are also provided. One method includes providing high voltage, via the GBL, to the paired sectors during erase and program operations and providing low voltage, via a local bit line, to each memory device during read operations.Type: GrantFiled: October 29, 2013Date of Patent: December 9, 2014Assignee: Cypress Semiconductor CorporationInventors: Ryan Tasuo Hirose, Bogdan I. Georgescu, Ashish Ashok Amonkar, Vijay Raghavan, Cristinel Zonte, Sean B. Mulholland
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Patent number: 8773913Abstract: Memory circuits and systems are provided. One memory circuit includes an active memory device, an inactive memory device, and a sense amplifier coupled between the active memory device and the inactive memory device. A reference current is coupled between the inactive memory device and the sense amplifier. The active memory device and the inactive memory device are the same type of memory device and the inactive memory device is a reference device with respect to the active memory device's current. A memory system includes a plurality of the above memory circuit coupled to one another. Methods for sensing current in a memory circuit are also provided. One method includes supplying power to a first memory device and comparing the amount of current in the first memory device and a reference current coupled to a second memory device that is the same type of memory device as the first memory device.Type: GrantFiled: December 29, 2011Date of Patent: July 8, 2014Assignee: Cypress Semiconductor CorporationInventors: Cristinel Zonte, Vijay Raghavan