Abstract: Methods are described for fabricating HIT solar cells, including double heterojunction and hybrid heterojunction-homojunction solar cells, with very thin single crystal silicon wafers, where the silicon wafer may be less than 80 microns thick, and even less than 50 microns thick. The methods overcome potential issues with handling these very thin wafers by using a process including epitaxial silicon deposition on a growth substrate, partial cell fabrication, attachment to a support substrate and then separation from the growth substrate. Some embodiments of the present invention may include a solar cell device architecture comprising the combination of a heterostructure on the front side of the device with a homojunction at the rear of the device. Furthermore, device performance may be enhanced by including a dielectric stack on the backside of the device for reflecting long wavelength infrared radiation.

Abstract: A design and manufacturing method for an interdigitated backside contact photovoltaic (PV) solar cell less than 100 ?m thick are disclosed. A porous silicon layer is formed on a wafer substrate. Portions of the PV cell are then formed using diffusion, epitaxy and autodoping from the substrate. All backside processing of the solar cell (junctions, passivation layer, metal contacts to the N+ and P+ regions) is performed while the thin epitaxial layer is attached to the porous layer and substrate. After backside processing, the wafer is clamped and exfoliated. The front of the PV cell is completed from the region of the wafer near the exfoliation fracture layer, with subsequent removal of the porous layer, texturing, passivation and deposition of an antireflective coating. During manufacturing, the cell is always supported by either the bulk wafer or a wafer chuck, with no processing of bare thin PV cells.

Abstract: An epitaxial reactor enabling simultaneous deposition of thin films on a multiplicity of wafers is disclosed. During deposition, a number of wafers are contained within a wafer sleeve comprising a number of wafer carrier plates spaced closely apart to minimize the process volume. Process gases flow preferentially into the interior volume of the wafer sleeve, which is heated by one or more lamp modules. Purge gases flow outside the wafer sleeve within a reactor chamber to minimize wall deposition. In addition, sequencing of the illumination of the individual lamps in the lamp module may further improve the linearity of variation in deposition rates within the wafer sleeve. To improve uniformity, the direction of process gas flow may be varied in a cross-flow configuration. Combining lamp sequencing with cross-flow processing in a multiple reactor system enables high throughput deposition with good film uniformities and efficient use of process gases.