Patents by Inventor Cui WEI

Cui WEI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9349825
    Abstract: A method for manufacturing a graphene transistor based on self-aligning technology, the method comprising: on a substrate (1), forming sequentially graphene material (4), a metal film (5), and photoresist patterns (6) formed by lithography, removing the metal film and the graphene material uncovered by the photoresist, forming an active area, and metal electrodes (7, 8, 9) of a source, a gate, and a drain of the transistor, wherein the source electrode 7 and drain electrode 9 are connected with a metal of the active region, and forming gate photoresist patterns (10) between the source and the drain by lithography, etching off the exposed metal, forming sequentially a seed layer (11), a gate dielectric layer (12), and gate metal (13) on the exposed graphene surface, and finally forming a graphene transistor.
    Type: Grant
    Filed: July 4, 2013
    Date of Patent: May 24, 2016
    Assignee: THE 13TH RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION
    Inventors: Zhihong Feng, Jia Li, Cui Wei, Qingbin Liu, Zezhao He, Jingjing Wang
  • Publication number: 20150364567
    Abstract: A method for manufacturing a graphene transistor based on self-aligning technology, the method comprising: on a substrate (1), forming sequentially graphene material (4), a metal film (5), and photoresist patterns (6) formed by lithography, removing the metal film and the graphene material uncovered by the photoresist, forming an active area, and metal electrodes (7, 8, 9) of a source, a gate, and a drain of the transistor, wherein the source electrode 7 and drain electrode 9 are connected with a metal of the active region, and forming gate photoresist patterns (10) between the source and the drain by lithography, etching off the exposed metal, forming sequentially a seed layer (11), a gate dielectric layer (12), and gate metal (13) on the exposed graphene surface, and finally forming a graphene transistor.
    Type: Application
    Filed: July 4, 2013
    Publication date: December 17, 2015
    Inventors: Zhihong FENG, Jia LI, Cui WEI, Qingbin LIU, Zezhao HE, Jingjing WANG