Patents by Inventor Cui Yin

Cui Yin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and structure for integrated stacked capacitor formation
    Patent number: 7250350
    Abstract: An integrated circuit device structure (and methods). The structure includes a semiconductor substrate comprising a surface. A first doped polysilicon liner is defined within a first trench region formed on a first plug coupled to the surface of the substrate and a second doped polysilicon liner is defined within a second trench region on a second plug coupled to the surface of the substrate. The first trench region is separated from the second trench region by a predetermined dimension. The structure also has a first rugged polysilicon material overlying surfaces of the first doped polysilicon material within the first trench region and a second rugged polysilicon material overlying surfaces of the second doped polysilicon material in the second trench region. The first rugged polysilicon material is free from a possibility of electrical contact with the second rugged polysilicon material.
    Type: Grant
    Filed: August 27, 2004
    Date of Patent: July 31, 2007
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Liu Yong, Cui Yin
  • Method and structure for integrated stacked capacitor formation
    Publication number: 20050287757
    Abstract: An integrated circuit device structure (and methods). The structure includes a semiconductor substrate comprising a surface. A first doped polysilicon liner is defined within a first trench region formed on a first plug coupled to the surface of the substrate and a second doped polysilicon liner is defined within a second trench region on a second plug coupled to the surface of the substrate. The first trench region is separated from the second trench region by a predetermined dimension. The structure also has a first rugged polysilicon material overlying surfaces of the first doped polysilicon material within the first trench region and a second rugged polysilicon material overlying surfaces of the second doped polysilicon material in the second trench region. The first rugged polysilicon material is free from a possibility of electrical contact with the second rugged polysilicon material.
    Type: Application
    Filed: August 27, 2004
    Publication date: December 29, 2005
    Applicant: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Liu Yong, Cui Yin